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ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/GPIOs

< ORCA SOM‎ | ORCA Evaluation Kit
History
Version Issue Date Notes
1.0.0 Dec 2021 First release


Contents

GPIOs interfaceEdit

DescriptionEdit

The GPIOs interface is available on the Evaluation Kit at the connector J8.

J8 is a 20x2x2.54mm pin strip header connector.


 
GPIOs connector (J8)

SignalsEdit

The following table describes the interface signals:

Pin# SOM Pin# Pin name Pin function Pin Notes
7 J15.150 SAI2_TXFS GPIO4_IO24
8 J15.144 SAI2_RXFS GPIO4_IO21
10 J15.140 SAI2_RXC GPIO4_IO22
11 J15.142 SAI2_RXD0 GPIO4_IO23
12 J15.146 SAI2_TXC GPIO4_IO25
13 J15.132 SPDIF_RX GPIO5_IO04
15 J15.134 SPDIF_TX GPIO5_IO03
16 J15.148 SAI2_TXD0 GPIO4_IO26
18 J15.138 SAI2_MCLK GPIO4_IO27
19 J15.122 ECSPI2_MOSI GPIO5_IO11
21 J15.120 ECSPI2_MISO GPIO5_IO12
22 J15.166 SAI5_MCLK GPIO3_IO25
23 J15.124 ECSPI2_SCLK GPIO5_IO10
24 J15.126 ECSPI2_SS0 GPIO5_IO13
26 J15.130 SPDIF_EXT_CLK GPIO5_IO05
27 J15.248 UART2_RXD GPIO5_IO24
28 J15.152 SAI3_MCLK GPIO5_IO02
29 J15.250 UART2_TXD GPIO5_IO25
31 J15.256 UART4_RXD GPIO5_IO28
32 J15.178 SAI5_RXFS GPIO3_IO19
33 J15.258 UART4_TXD GPIO5_IO29
35 J15.176 SAI5_RXD3 GPIO3_IO24
36 J15.174 SAI5_RXD2 GPIO3_IO23
37 J15.172 SAI5_RXD1 GPIO3_IO22
38 J15.170 SAI5_RXD0 GPIO3_IO21
40 J15.168 SAI5_RXC GPIO3_IO20
1, 17 - 3V3_CB +3.3V BOARD_PGOOD driven rail
2, 4 - 5V_VIN +5V Always powered
6, 9, 14, 20, 25, 30, 34, 39 - DGND Ground

All the GPIO signals are 0-3.3V level.

Device mappingEdit

GPIOs are mapped into banks each of which contains 32 pins. They are named as GPIO<bank>_IO<pin>

Each pin can be addressed with an incremental number, calculated as follows: GPIO = 32 x (<bank> - 1) + <pin>

Device usageEdit

Under Linux the GPIOs can be manipulated su sysfs export or with the gpio tools.