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Implementation
D1 and D2 communicates through the [https://en.wikipedia.org/wiki/RPMsg RPMsg protocol]. On the Cortex M7 side, the [https://github.com/NXPmicro/rpmsg-lite RPMsg Lite] implementation by NXP was used. The interface between D1 and D2 comprises a shared memory buffer as well. This area is used to exchange audio samples. Synchronization messages are exchanged over RPMsg channels instead.
For the sake of simplicity, the audio samples are not captured by the Cortex M7 with a real microphone. They are retrieved by prefilled memory buffers that can not be accessed by Cortex A53 cores. For the purposes of discussion, this simplification is neglectable as the communication mechanisms between the domains are not affected at all. To this endstore the audio samples, a reserved buffer is also allocated in the SDRAM bank. In this example, reservation reserved allocation is implemented at Linux device tree level. It is worth remembering that, to restrict accessibility, it is also possible to make use of a hardware-based, stronger mechanism thank to the i.MX8M Plus Resource Domain Controller (RDC). The inference application (IAPP) running in D1 uses a simple sysfs-based interface to interact with the firmware running in D2. Basically, it works like this:* IAPP triggers the "acquisition" of audio samples by writing to a specific sysfs pseudo file* The Cortex M7 firmware (MFW)** retrieves randomly one of the prefilled audio buffers** adds some noise to the samples** stores the resulting buffer in the shared memory** signals IAPP the buffer is ready** IAPP runs the inference to spot the pronounced word. == Additional notes regarding the inference application ==TBD
=Testing=
==Boot sequence==
This example was arranged in order to execute the following boot sequence:
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