MITO 8M SOM/MITO 8M Hardware/Power and Reset/Reset scheme and control signals
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Contents
Reset scheme and control signals[edit | edit source]
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:
- MRST
- POR
- SNVS
- SYSRST
- ...
TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI
TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM
NVCC_VSNVS[edit | edit source]
Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS (aka 3.3VIN).
Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.
EXT_RESET[edit | edit source]
EXT_RESET is internally pulled-up with a 90kΩ to NVCC_VSNVS. Connect EXT_RESET signal to DGND (for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output.
This will power down the VDD_SOC_0V9 and make PMIC_ON pulled low by PG (Power Good) of VDD_SOC_0V9 regulator.
Since PMIC_ON serves as the enable signal of PMIC and other discrete power supply chips, all the power supplies except for the SNVS domain will be OFF.
The RESETn will keep asserted for 270 ms after EXT_RESET is released, thus providing enough time for the power supplies to be completely powered down. During this time, the POR_B driven by the PMIC will also keep asserted (low).
After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.
CPU_PORn[edit | edit source]
The following devices can assert this active-low signal:
- PMIC
- multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
CPU_ONOFF[edit | edit source]
CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS.
Handling CPU-initiated software reset[edit | edit source]
By default, MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly.
For these reasons it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in DESK-MX8. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT to assert the WDOG_B signal. This signal in turn is routed to the GPIO1_IO02 pad. At the hardware level, this signal is AC-coupled to the master reset pin of the internal supervisor IC. It acts as a complete hardware reset by the assertion of its RESETn output (on the same way of EXT_RESET pin).
