Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

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===Pinout Table J4 pins declaration ===
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===Pinout Table J5 pins declaration ===
  
 
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[[Category:MITO 8M]]
 
[[Category:MITO 8M]]

Revision as of 12:18, 24 September 2020

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History
Version Issue Date Notes
1.0.0 Sep 2020 First release


Pinout Table[edit | edit source]

Introduction[edit | edit source]

This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the Axel Ultra components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC
  • LAN.<x> : pin connected to the LAN PHY
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
  • SV.<x>: pin connected to voltage supervisor
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6 NVCC_3V3 I/O
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7 NVCC_3V3 I/O
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6 NVCC_3V3 I/O
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6 NVCC_3V3 I/O
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5 NVCC_3V3 I/O
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5 NVCC_3V3 I/O
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7 NVCC_3V3 I/O
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7 NVCC_3V3 I/O
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5 NVCC_3V3 I/O
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5 NVCC_3V3 I/O
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7 NVCC_3V3 I/O
J1.63 I2C2_SCL CPU.I2C2_SCL G7 NVCC_3V3 I/O
J1.65 I2C2_SDA CPU.I2C2_SDA F7 NVCC_3V3 I/O
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5 NVCC_3V3 I/O
J1.69 SAI2_RXC CPU.SAI2_RXC H3 NVCC_3V3 I/O
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4 NVCC_3V3 I/O
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22 NVCC_3V3 I/O
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21 NVCC_3V3 I/O
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22 NVCC_3V3 I/O
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21 NVCC_3V3 I/O
J1.83 SD2_CMD CPU.SD2_CMD M22 NVCC_3V3 I/O
J1.85 SD2_CLK CPU.SD2_CLK L22 NVCC_3V3 I/O
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7 NVCC_3V3 I/O
J1.91 UART3_RXD CPU.UART3_RXD A6 NVCC_3V3 I/O
J1.93 UART4_TXD CPU.UART4_TXD D7 NVCC_3V3 I/O
J1.95 UART4_RXD CPU.UART4_RXD C6 NVCC_3V3 I/O
J1.97 SD2_WP CPU.SD2_WP M21 NVCC_3V3 I/O
J1.99 SD2_RST_B CPU.SD2_RESET_B R22 NVCC_3V3 I/O
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3 VDD_PHY_1V8 I/O
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3 VDD_PHY_1V8 I/O
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 - D connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 - D connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 - D connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 - D connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 - D connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 - D connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 - D connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 - D connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 - D connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 - D connected with capacitor in series
J1.127 HDMI_CEC CPU.HDMI_CEC W3 VDD_PHY_1V8 I/O
J1.129 HDMI_HPD CPU.HDMI_HPD W2 VDD_PHY_1V8 I/O
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B L21 NVCC_3V3 I/O
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 D4 NVCC_3V3 I/O
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D5 NVCC_3V3 I/O
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO B4 NVCC_3V3 I/O
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 P4 NVCC_3V3 I/O
J1.187 UART1_TXD ??? NVCC_3V3 I/O
J1.189 UART1_RXD ??? NVCC_3V3 I/O
J1.191 UART2_TXD ??? NVCC_3V3 I/O
J1.193 UART2_RXD ??? NVCC_3V3 I/O
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI A4 NVCC_3V3 I/O
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 K7 NVCC_3V3 I/O
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 P5 NVCC_3V3 I/O
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 L7 NVCC_3V3 I/O
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30 - S
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS I internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
J1.24 EXT_RESET MASTER RESET - - I internal pull-up to NVCC_SNVS
J1.26 SAI3_RXC CPU.SAI3_RXC F4 NVCC_3V3 I/O
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 R4 NVCC_3V3 I/O
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD F3 NVCC_3V3 I/O
J1.34 SAI2_MCLK CPU.SAI2_MCLK H5 NVCC_3V3 I/O
J1.36 SAI3_RXFS CPU.SAI3_RXFS G4 NVCC_3V3 I/O
J1.38 I2C3_SCL CPU.I2C3_SCL G8 NVCC_3V3 I/O
J1.40 SAI3_TXFS CPU.SAI3_TXFS G3 NVCC_3V3 I/O
J1.42 SPDIF_RX CPU.SPDIF_RX G6 NVCC_3V3 I/O
J1.44 SPDIF_TX CPU.SPDIF_TX F6 NVCC_3V3 I/O
J1.46 SAI3_MCLK CPU.SAI3_MCLK D3 NVCC_3V3 I/O
J1.48 I2C3_SDA CPU.I2C3_SDA E9 NVCC_3V3 I/O
J1.50 SAI3_TXC CPU.SAI3_TXC C4 NVCC_3V3 I/O
J1.52 SAI3_TXD CPU.SAI3_TXD C3 NVCC_3V3 I/O
J1.54 SD1_STROBE CPU.SD1_STROBE T24 NVCC_1V8 // NVCC_3V3 ??? I/O internally used for eMMC
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK K4 NVCC_3V3 I/O
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 J6 NVCC_3V3 I/O
J1.62 SAI5_RXFS CPU.SAI5_RXFS N4 NVCC_3V3 I/O
J1.64 SAI5_RXC CPU.SAI5_RXC L5 NVCC_3V3 I/O
J1.66 SAI2_TXC CPU.SAI2_TXC J5 NVCC_3V3 I/O
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 G5 NVCC_3V3 I/O
J1.70 SAI2_TXFS CPU.SAI2_TXFS H4 NVCC_3V3 I/O
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 H6 NVCC_3V3 I/O
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 M5 NVCC_3V3 I/O
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 L4 NVCC_3V3 I/O
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 M4 NVCC_3V3 I/O
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 K5 NVCC_3V3 I/O
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N T22 VDDA_1V8 D
J1.86 CLK2_P CPU.CLK2_P U22 VDDA_1V8 D
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N K24 VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P K25 VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N H24 VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P H25 VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N J24 VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P J25 VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N A22 - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P B22 - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N A23 - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P B23 - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N C22 - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P D22 - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N B24 - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P C23 - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N C21 - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P D21 - D
J1.122 DGND DGND - - G
J1.124 NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O internally used for NAND
J1.126 NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O internally used for NAND
J1.128 NAND_CE0_B // SD1_CLK CPU.NAND_CE0_B // CPU.SD1_CLK H19 // L25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.130 NAND_CE1_B // SD1_CMD CPU.NAND_CE1_B // CPU.SD1_CMD G21 // L24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.132 NAND_CE2_B // SD1_RST_B CPU.NAND_CE2_B // CPU.SD1_RST_B F21 // R24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.134 NAND_CE3_B // SD1_STROBE CPU.NAND_CE3_B // CPU.SD1_STROBE H20 // T24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.136 NAND_CLE DGND H21 NVCC_3V3 I/O
J1.138 NAND_DATA00 // SD1_DATA0 CPU.NAND_DATA00 // CPU.SD1_DATA0 G20 // M25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.140 NAND_DATA01 // SD1_DATA1 CPU.NAND_DATA01 // CPU.SD1_DATA1 J20 // M24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.142 NAND_DATA02 // SD1_DATA2 CPU.NAND_DATA02 // CPU.SD1_DATA2 H22 // N25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.144 NAND_DATA03 // SD1_DATA3 CPU.NAND_DATA03 // CPU.SD1_DATA3 J21 // P25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.146 DGND DGND - - G
J1.148 NAND_DATA04 // SD1_DATA4 CPU.NAND_DATA04 // CPU.SD1_DATA4 L20 // N24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.150 NAND_DATA05 // SD1_DATA5 CPU.NAND_DATA05 // CPU.SD1_DATA5 J22 // P24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.152 NAND_DATA06 // SD1_DATA6 CPU.NAND_DATA06 // CPU.SD1_DATA6 L19 // R25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.154 NAND_DATA07 // SD1_DATA7 CPU.NAND_DATA07 // CPU.SD1_DATA7 M19 // T25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.156 NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O
J1.158 NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O
J1.160 NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O
J1.162 NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O
J1.164 DGND DGND - - G
J1.166 CLK1_N CPU.CLK1_N T23 D
J1.168 CLK1_P CPU.CLK1_P R23 D
J1.170 USB2_RXN CPU.USB2_RX_N B8 D
J1.172 USB2_RXP CPU.USB2_RX_P A8 D
J1.174 USB2_TXN CPU.USB2_TX_N B9 D
J1.176 USB2_TXP CPU.USB2_TX_P A9 D
J1.178 USB1_RXN CPU.USB1_RX_N B12 D
J1.180 USB1_RXP CPU.USB1_RX_P A12 D
J1.182 USB1_TXN CPU.USB1_TX_N B13 D
J1.184 USB1_TXP CPU.USB1_TX_P A13 D
J1.186 USB1_VBUS CPU.USB1_VBUS D14 - S
J1.188 USB2_VBUS CPU.USB2_VBUS D9 - S
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C14 VDD_PHY_3V3 I
J1.194 USB2_ID CPU.USB2_ID C9 VDD_PHY_3V3 I
J1.196 USB1_DN CPU.USB1_DN B14 - D
J1.198 USB1_DP CPU.USB1_DP A14 - D
J1.200 USB2_DP CPU.USB2_DP A10 - D
J1.202 USB2_DN CPU.USB2_DN B10 - D
J1.204 DGND DGND - - G

Pinout Table J4 pins declaration[edit | edit source]

Pinout Table J5 pins declaration[edit | edit source]

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