Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

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(→‎Pinout Table ODD pins declaration)
(→‎Pinout Table EVEN pins declaration)
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|NAND_DATA06  //  SD1_DATA6
 
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|NAND_DATA07  //  SD1_DATA7
 
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|NAND_READY_B
 
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|NAND_WE_B
 
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|NAND_WP_B
 
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|CLK1_N
 
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|CLK1_P
 
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|USB2_RXN
 
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|USB2_RXP
 
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|J1.174
 
|J1.174
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|USB2_TXN
 
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Line 1,799: Line 1,799:
 
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|J1.176
 
|J1.176
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|USB2_TXP
 
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|J1.178
 
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|USB1_RXN
 
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|J1.180
 
|J1.180
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|USB1_RXP
 
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Line 1,826: Line 1,826:
 
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|J1.182
 
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|USB1_TXN
 
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Line 1,835: Line 1,835:
 
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|J1.184
 
|J1.184
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|USB1_TXP
 
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Line 1,844: Line 1,844:
 
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|J1.186
 
|J1.186
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|USB1_VBUS
 
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Line 1,853: Line 1,853:
 
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Line 1,862: Line 1,862:
 
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|J1.190
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|DGND
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|<nowiki>-</nowiki>
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|G
 
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|J1.192
 
|J1.192
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|USB1_ID
 
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Line 1,880: Line 1,880:
 
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|J1.194
 
|J1.194
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|USB2_ID
 
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Line 1,889: Line 1,889:
 
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|J1.196
 
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|USB1_DN
 
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Line 1,898: Line 1,898:
 
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|J1.198
 
|J1.198
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|USB1_DP
 
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Line 1,907: Line 1,907:
 
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|J1.200
 
|J1.200
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|USB2_DP
 
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Line 1,916: Line 1,916:
 
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|J1.202
 
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|USB2_DN
 
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Line 1,925: Line 1,925:
 
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|J1.204
 
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|DGND
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| -
−
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|<nowiki>-</nowiki>
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|G
 
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Revision as of 09:12, 24 September 2020

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History
Version Issue Date Notes
1.0.0 Sep 2020 First release


Pinout Table[edit | edit source]

Introduction[edit | edit source]

This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the Axel Ultra components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC
  • LAN.<x> : pin connected to the LAN PHY
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6 NVCC_3V3 I/O
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7 NVCC_3V3 I/O
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6 NVCC_3V3 I/O
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6 NVCC_3V3 I/O
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5 NVCC_3V3 I/O
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5 NVCC_3V3 I/O
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7 NVCC_3V3 I/O
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7 NVCC_3V3 I/O
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5 NVCC_3V3 I/O
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5 NVCC_3V3 I/O
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7 NVCC_3V3 I/O
J1.63 I2C2_SCL CPU.I2C2_SCL G7 NVCC_3V3 I/O
J1.65 I2C2_SDA CPU.I2C2_SDA F7 NVCC_3V3 I/O
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5 NVCC_3V3 I/O
J1.69 SAI2_RXC CPU.SAI2_RXC H3 NVCC_3V3 I/O
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4 NVCC_3V3 I/O
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22 NVCC_3V3 I/O
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21 NVCC_3V3 I/O
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22 NVCC_3V3 I/O
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21 NVCC_3V3 I/O
J1.83 SD2_CMD CPU.SD2_CMD M22 NVCC_3V3 I/O
J1.85 SD2_CLK CPU.SD2_CLK L22 NVCC_3V3 I/O
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7 NVCC_3V3 I/O
J1.91 UART3_RXD CPU.UART3_RXD A6 NVCC_3V3 I/O
J1.93 UART4_TXD CPU.UART4_TXD D7 NVCC_3V3 I/O
J1.95 UART4_RXD CPU.UART4_RXD C6 NVCC_3V3 I/O
J1.97 SD2_WP CPU.SD2_WP M21 NVCC_3V3 I/O
J1.99 SD2_RST_B CPU.SD2_RESET_B R22 NVCC_3V3 I/O
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3 VDD_PHY_1V8 I/O
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3 VDD_PHY_1V8 I/O
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 - D connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 - D connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 - D connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 - D connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 - D connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 - D connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 - D connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 - D connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 - D connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 - D connected with capacitor in series
J1.127 HDMI_CEC CPU.HDMI_CEC W3 VDD_PHY_1V8 I/O
J1.129 HDMI_HPD CPU.HDMI_HPD W2 VDD_PHY_1V8 I/O
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B L21 NVCC_3V3 I/O
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 D4 NVCC_3V3 I/O
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D5 NVCC_3V3 I/O
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO B4 NVCC_3V3 I/O
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 P4 NVCC_3V3 I/O
J1.187 UART1_TXD ?? NVCC_3V3 I/O
J1.189 UART1_RXD ?? NVCC_3V3 I/O
J1.191 UART2_TXD ?? NVCC_3V3 I/O
J1.193 UART2_RXD ?? NVCC_3V3 I/O
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI A4 NVCC_3V3 I/O
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 K7 NVCC_3V3 I/O
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 P5 NVCC_3V3 I/O
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 L7 NVCC_3V3 I/O
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD
J1.20 BOOT_MODE_SEL
J1.22 CPU_PORn
J1.24 EXT_RESET
J1.26 SAI3_RXC
J1.28 GPIO1_IO02
J1.30 DGND DGND - - G
J1.32 SAI3_RXD
J1.34 SAI2_MCLK
J1.36 SAI3_RXFS
J1.38 I2C3_SCL
J1.40 SAI3_TXFS
J1.42 SPDIF_RX
J1.44 SPDIF_TX
J1.46 SAI3_MCLK
J1.48 I2C3_SDA
J1.50 SAI3_TXC
J1.52 SAI3_TXD
J1.54 SD1_STROBE
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK
J1.60 GPIO1_IO15
J1.62 SAI5_RXFS
J1.64 SAI5_RXC
J1.66 SAI2_TXC
J1.68 SAI2_TXD0
J1.70 SAI2_TXFS
J1.72 SAI2_RXD0
J1.74 SAI5_RXD0
J1.76 SAI5_RXD1
J1.78 SAI5_RXD2
J1.80 SAI5_RXD3
J1.82 DGND DGND - - G
J1.84 CLK2_N
J1.86 CLK2_P
J1.88 PCIE1_REF_PAD_CLK_N
J1.90 PCIE1_REF_PAD_CLK_P
J1.92 PCIE1_RXN_N
J1.94 PCIE1_RXN_P
J1.96 PCIE1_TXN_N
J1.98 PCIE1_TXN_P
J1.100 DGND DGND - - G
J1.102 MIPI_CSI1_CLK_N
J1.104 MIPI_CSI1_CLK_P
J1.106 MIPI_CSI1_D0_N
J1.108 MIPI_CSI1_D0_P
J1.110 MIPI_CSI1_D1_N
J1.112 MIPI_CSI1_D1_P
J1.114 MIPI_CSI1_D2_N
J1.116 MIPI_CSI1_D2_P
J1.118 MIPI_CSI1_D3_N
J1.120 MIPI_CSI1_D3_P
J1.122 DGND DGND - - G
J1.124 NAND_DQS
J1.126 NAND_ALE
J1.128 NAND_CE0_B // SD1_CLK
J1.130 NAND_CE1_B // SD1_CMD
J1.132 NAND_CE2_B // SD1_RST_B
J1.134 NAND_CE3_B // SD1_STROBE
J1.136 NAND_CLE
J1.138 NAND_DATA00 // SD1_DATA0
J1.140 NAND_DATA01 // SD1_DATA1
J1.142 NAND_DATA02 // SD1_DATA2
J1.144 NAND_DATA03 // SD1_DATA3
J1.146 DGND DGND - - G
J1.148 NAND_DATA04 // SD1_DATA4
J1.150 NAND_DATA05 // SD1_DATA5
J1.152 NAND_DATA06 // SD1_DATA6
J1.154 NAND_DATA07 // SD1_DATA7
J1.156 NAND_RE_B
J1.158 NAND_READY_B
J1.160 NAND_WE_B
J1.162 NAND_WP_B
J1.164 DGND DGND - - G
J1.166 CLK1_N
J1.168 CLK1_P
J1.170 USB2_RXN
J1.172 USB2_RXP
J1.174 USB2_TXN
J1.176 USB2_TXP
J1.178 USB1_RXN
J1.180 USB1_RXP
J1.182 USB1_TXN
J1.184 USB1_TXP
J1.186 USB1_VBUS
J1.188 USB2_VBUS
J1.190 DGND DGND - - G
J1.192 USB1_ID
J1.194 USB2_ID
J1.196 USB1_DN
J1.198 USB1_DP
J1.200 USB2_DP
J1.202 USB2_DN
J1.204 DGND DGND - - G
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