Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

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(→‎Introduction)
(→‎Pinout Table ODD pins declaration)
Line 247: Line 247:
 
|J1.37
 
|J1.37
 
|GPIO1_IO00
 
|GPIO1_IO00
−
|
+
|CPU.GPIO1_IO00
−
|
+
|T6
 
|
 
|
 
|
 
|
Line 256: Line 256:
 
|J1.39
 
|J1.39
 
|GPIO1_IO01
 
|GPIO1_IO01
−
|
+
|CPU.GPIO1_IO01
−
|
+
|T7
 
|
 
|
 
|
 
|
Line 264: Line 264:
 
|-
 
|-
 
|J1.41
 
|J1.41
−
|SPDIF_EXT_CLK (PWM1_OUT)
+
|SPDIF_EXT_CLK
−
|
+
|CPU.SPDIF_EXT_CLK
−
|
+
|E6
 
|
 
|
 
|
 
|
Line 274: Line 274:
 
|J1.43
 
|J1.43
 
|GPIO1_IO13
 
|GPIO1_IO13
−
|
+
|CPU.GPIO1_IO13
−
|
+
|K6
 
|
 
|
 
|
 
|
Line 291: Line 291:
 
|-
 
|-
 
|J1.47
 
|J1.47
−
|ECSPI2_SCLK (UART4_RX)
+
|ECSPI2_SCLK
−
|
+
|CPU.ECSPI2_SCLK
−
|
+
|C5
 
|
 
|
 
|
 
|
Line 300: Line 300:
 
|-
 
|-
 
|J1.49
 
|J1.49
−
|ECSPI2_MOSI (UART4_TX)
+
|ECSPI2_MOSI
−
|
+
|CPU.ECSPI2_MOSI
−
|
+
|E5
 
|
 
|
 
|
 
|
Line 310: Line 310:
 
|J1.51
 
|J1.51
 
|GPIO1_IO08
 
|GPIO1_IO08
−
|
+
|CPU.GPIO1_IO08
−
|
+
|N7
 
|
 
|
 
|
 
|
Line 319: Line 319:
 
|J1.53
 
|J1.53
 
|GPIO1_IO09
 
|GPIO1_IO09
−
|
+
|CPU.GPIO1_IO09
−
|
+
|M7
 
|
 
|
 
|
 
|
Line 327: Line 327:
 
|-
 
|-
 
|J1.55
 
|J1.55
−
|ECSPI2_MISO (UART4_CTS_B)
+
|ECSPI2_MISO
−
|
+
|CPU.ECSPI2_MISO
−
|
+
|B5
 
|
 
|
 
|
 
|
Line 345: Line 345:
 
|-
 
|-
 
|J1.59
 
|J1.59
−
|ECSPI2_SS0 (UART4_RTS_B)
+
|ECSPI2_SS0
−
|
+
|CPU.ECSPI2_SS0
−
|
+
|A5
 
|
 
|
 
|
 
|
Line 355: Line 355:
 
|J1.61
 
|J1.61
 
|GPIO1_IO05
 
|GPIO1_IO05
−
|
+
|CPU.GPIO1_IO05
−
|
+
|P7
 
|
 
|
 
|
 
|
Line 364: Line 364:
 
|J1.63
 
|J1.63
 
|I2C2_SCL
 
|I2C2_SCL
−
|
+
|CPU.I2C2_SCL
−
|
+
|G7
 
|
 
|
 
|
 
|
Line 373: Line 373:
 
|J1.65
 
|J1.65
 
|I2C2_SDA
 
|I2C2_SDA
−
|
+
|CPU.I2C2_SDA
−
|
+
|F7
 
|
 
|
 
|
 
|
Line 382: Line 382:
 
|J1.67
 
|J1.67
 
|GPIO1_IO06
 
|GPIO1_IO06
−
|
+
|CPU.GPIO1_IO06
−
|
+
|N5
 
|
 
|
 
|
 
|
Line 391: Line 391:
 
|J1.69
 
|J1.69
 
|SAI2_RXC
 
|SAI2_RXC
−
|
+
|CPU.SAI2_RXC
−
|
+
|H3
 
|
 
|
 
|
 
|
Line 400: Line 400:
 
|J1.71
 
|J1.71
 
|SAI2_RXFS
 
|SAI2_RXFS
−
|
+
|CPU.SAI2_RXFS
−
|
+
|J4
 
|
 
|
 
|
 
|
Line 418: Line 418:
 
|J1.75
 
|J1.75
 
|SD2_DATA0
 
|SD2_DATA0
−
|
+
|CPU.SD2_DATA0
−
|
+
|N22
 
|
 
|
 
|
 
|
Line 427: Line 427:
 
|J1.77
 
|J1.77
 
|SD2_DATA1
 
|SD2_DATA1
−
|
+
|CPU.SD2_DATA1
−
|
+
|N21
 
|
 
|
 
|
 
|
Line 436: Line 436:
 
|J1.79
 
|J1.79
 
|SD2_DATA2
 
|SD2_DATA2
−
|
+
|CPU.SD2_DATA2
−
|
+
|P22
 
|
 
|
 
|
 
|
Line 445: Line 445:
 
|J1.81
 
|J1.81
 
|SD2_DATA3
 
|SD2_DATA3
−
|
+
|CPU.SD2_DATA03
−
|
+
|P21
 
|
 
|
 
|
 
|
Line 454: Line 454:
 
|J1.83
 
|J1.83
 
|SD2_CMD
 
|SD2_CMD
−
|
+
|CPU.SD2_CMD
−
|
+
|M22
 
|
 
|
 
|
 
|
Line 463: Line 463:
 
|J1.85
 
|J1.85
 
|SD2_CLK
 
|SD2_CLK
−
|
+
|CPU.SD2_CLK
−
|
+
|L22
 
|
 
|
 
|
 
|
Line 481: Line 481:
 
|J1.89
 
|J1.89
 
|UART3_TXD
 
|UART3_TXD
−
|
+
|CPU.UART3_TXD
−
|
+
|B7
 
|
 
|
 
|
 
|
Line 490: Line 490:
 
|J1.91
 
|J1.91
 
|UART3_RXD
 
|UART3_RXD
−
|
+
|CPU.UART3_RXD
−
|
+
|A6
 
|
 
|
 
|
 
|
Line 499: Line 499:
 
|J1.93
 
|J1.93
 
|UART4_TXD
 
|UART4_TXD
−
|
+
|CPU.UART4_TXD
−
|
+
|D7
 
|
 
|
 
|
 
|
Line 508: Line 508:
 
|J1.95
 
|J1.95
 
|UART4_RXD
 
|UART4_RXD
−
|
+
|CPU.UART4_RXD
−
|
+
|C6
 
|
 
|
 
|
 
|
Line 517: Line 517:
 
|J1.97
 
|J1.97
 
|SD2_WP
 
|SD2_WP
−
|
+
|CPU.SD2_WP
−
|
+
|M21
 
|
 
|
 
|
 
|
Line 526: Line 526:
 
|J1.99
 
|J1.99
 
|SD2_RST_B
 
|SD2_RST_B
−
|
+
|CPU.SD2_RESET_B
−
|
+
|R22
 
|
 
|
 
|
 
|
Line 535: Line 535:
 
|J1.101
 
|J1.101
 
|HDMI_DDC_SCL
 
|HDMI_DDC_SCL
−
|
+
|CPU.HDMI_DDC_SCL
−
|
+
|R3
 
|
 
|
 
|
 
|
Line 544: Line 544:
 
|J1.103
 
|J1.103
 
|HDMI_DDC_SDA
 
|HDMI_DDC_SDA
−
|
+
|CPU.HDMI_DDC_SDA
−
|
+
|P3
 
|
 
|
 
|
 
|
Line 553: Line 553:
 
|J1.105
 
|J1.105
 
|HDMI_AUX_N
 
|HDMI_AUX_N
 +
|CPU.HDMI_AUX_N
 +
|V2
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-
 
|J1.107
 
|J1.107
 
|HDMI_AUX_P
 
|HDMI_AUX_P
 +
|CPU.HDMI_AUX_P
 +
|V1
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-
Line 579: Line 579:
 
|-
 
|-
 
|J1.111
 
|J1.111
−
|HDMI_TX_N_LN_3
+
|HDMI_TX_M_LN_3
−
|
+
|CPU.HDMI_TX_M_LN_3
−
|
+
|M2
−
|
 
 
|
 
|
 
|
 
|
 +
|connected with capacitor in series
 
|
 
|
 
|-
 
|-
 
|J1.113
 
|J1.113
 
|HDMI_TX_P_LN_3
 
|HDMI_TX_P_LN_3
 +
|CPU.HDMI_TX_P_LN_3
 +
|M1
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-
 
|J1.115
 
|J1.115
−
|HDMI_TX_N_LN_0
+
|HDMI_TX_M_LN_0
−
|
+
|CPU.HDMI_TX_M_LN_0
−
|
+
|T2
−
|
 
 
|
 
|
 
|
 
|
 +
|connected with capacitor in series
 
|
 
|
 
|-
 
|-
 
|J1.117
 
|J1.117
 
|HDMI_TX_P_LN_0
 
|HDMI_TX_P_LN_0
 +
|CPU.HDMI_TX_P_LN_0
 +
|T1
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-
 
|J1.119
 
|J1.119
−
|HDMI_TX_N_LN_1
+
|HDMI_TX_M_LN_1
−
|
+
|CPU.HDMI_TX_M_LN_1
−
|
+
|U1
−
|
 
 
|
 
|
 
|
 
|
 +
|connected with capacitor in series
 
|
 
|
 
|-
 
|-
 
|J1.121
 
|J1.121
 
|HDMI_TX_P_LN_1
 
|HDMI_TX_P_LN_1
 +
|CPU.HDMI_TX_P_LN_1
 +
|U2
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-
 
|J1.123
 
|J1.123
−
|HDMI_TX_N_LN_2
+
|HDMI_TX_M_LN_2
−
|
+
|CPU.HDMI_TX_M_LN_2
−
|
+
|N1
−
|
 
 
|
 
|
 
|
 
|
 +
|connected with capacitor in series
 
|
 
|
 
|-
 
|-
 
|J1.125
 
|J1.125
 
|HDMI_TX_P_LN_2
 
|HDMI_TX_P_LN_2
 +
|CPU.HDMI_TX_P_LN_2
 +
|N2
 
|
 
|
 
|
 
|
−
|
+
|connected with capacitor in series
−
|
 
−
|
 
 
|
 
|
 
|-
 
|-

Revision as of 08:28, 24 September 2020

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History
Version Issue Date Notes
1.0.0 Sep 2020 First release


Pinout Table[edit | edit source]

Introduction[edit | edit source]

This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the Axel Ultra components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC
  • LAN.<x> : pin connected to the LAN PHY
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7
J1.63 I2C2_SCL CPU.I2C2_SCL G7
J1.65 I2C2_SDA CPU.I2C2_SDA F7
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5
J1.69 SAI2_RXC CPU.SAI2_RXC H3
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21
J1.83 SD2_CMD CPU.SD2_CMD M22
J1.85 SD2_CLK CPU.SD2_CLK L22
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7
J1.91 UART3_RXD CPU.UART3_RXD A6
J1.93 UART4_TXD CPU.UART4_TXD D7
J1.95 UART4_RXD CPU.UART4_RXD C6
J1.97 SD2_WP CPU.SD2_WP M21
J1.99 SD2_RST_B CPU.SD2_RESET_B R22
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 connected with capacitor in series
J1.127 HDMI_CEC
J1.129 HDMI_HPD
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B
J1.179 ECSPI1_SS0
J1.181 ECSPI1_SCLK
J1.183 ECSPI1_MISO
J1.185 GPIO1_IO03
J1.187 UART1_TXD
J1.189 UART1_RXD
J1.191 UART2_TXD
J1.193 UART2_RXD
J1.195 ECSPI1_MOSI
J1.197 GPIO1_IO14
J1.199 GPIO1_IO04
J1.201 GPIO1_IO12 (USB1_OTG_PWR)
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.2
J1.4
J1.6
J1.8
J1.10
J1.12
J1.14
J1.16
J1.18
J1.20
J1.22
J1.24
J1.26
J1.28
J1.30
J1.32
J1.34
J1.36
J1.38
J1.40
J1.42
J1.44
J1.46
J1.48
J1.50
J1.52
J1.54
J1.56
J1.58
J1.60
J1.62
J1.64
J1.66
J1.68
J1.70
J1.72
J1.74
J1.76
J1.78
J1.80
J1.82
J1.84
J1.86
J1.88
J1.90
J1.92
J1.94
J1.96
J1.98
J1.100
J1.102
J1.104
J1.106
J1.108
J1.110
J1.112
J1.114
J1.116
J1.118
J1.120
J1.122
J1.124
J1.126
J1.128
J1.130
J1.132
J1.134
J1.136
J1.138
J1.140
J1.142
J1.144
J1.146
J1.148
J1.150
J1.152
J1.154
J1.156
J1.158
J1.160
J1.162
J1.164
J1.166
J1.168
J1.170
J1.172
J1.174
J1.176
J1.178
J1.180
J1.182
J1.184
J1.186
J1.188
J1.190
J1.192
J1.194
J1.196
J1.198
J1.200
J1.202
J1.204
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