Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

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<section begin=History/>
+
<section begin="History" />
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
 
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|10368|2020/09/29}}
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
 
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
|-
 
|-
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
 
|-
 
|-
 
|}
 
|}
−
<section end=History/>
+
<section end="History" />
−
<section begin=Body/>
+
<section begin="Body" />
−
==Pinout Table==
+
==Connectors and Pinout Table description==
−
===Introduction===
 
  
−
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.
+
=== Connectors description ===
 +
In the following table are described all available connectors integrated on MITO 8M SOM:
 +
{| class="wikitable"
 +
|-
 +
!Connector name
 +
!Connector Type
 +
!Notes
 +
!Carrier board counterpart
 +
|-
 +
|J1
 +
|SODIMM edge connector 204 pin
 +
|partially compatible with [[AXEL Lite SOM]]
 +
|TE Connectivity 2-2013289-1
 +
|-
 +
|J4
 +
|ONE PIECE connector single row 25pins
 +
|
 +
|SAMTEC FSI-125-03-G-S-AD-TR
 +
|-
 +
|J5
 +
|ONE PIECE connector single row 25pins
 +
|
 +
|SAMTEC FSI-125-03-G-S-AD-TR
 +
|}
 +
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference:
 +
 
 +
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
 +
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
  
 +
Below a detailed description of the pinout, grouped in the following tables:
 +
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
 +
* a dedicated tables for J4 one-piece connector
 +
* a dedicated tables for J5 one-piece connector
 +
 +
=== Pinout Table description ===
 
Each row in the pinout tables contains the following information:
 
Each row in the pinout tables contains the following information:
−
 
+
{| class="wikitable"
−
{| class="wikitable" style="width:50%;"
 
 
|-
 
|-
 
|'''Pin'''
 
|'''Pin'''
Line 28: Line 59:
 
|-
 
|-
 
|'''Pin Name'''  
 
|'''Pin Name'''  
−
| Pin (signal) name on the AxelLite connectors
+
| Pin (signal) name on the MITO 8M connectors
 
|-
 
|-
 
|'''Internal<br>connections'''  
 
|'''Internal<br>connections'''  
−
| Connections to the Axel Ultra components
+
| Connections to the components
 
* CPU.<x> : pin connected to CPU pad named <x>
 
* CPU.<x> : pin connected to CPU pad named <x>
−
* PMIC.<x> : pin connected to the Power Manager IC
+
* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
−
* LAN.<x> : pin connected to the LAN PHY
+
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
−
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
+
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
−
* SV.<x>: pin connected to voltage supervisor
 
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
Line 70: Line 100:
 
|}
 
|}
  
−
===Pinout Table ODD pins declaration ===
+
==SODIMM J1 ODD pins declaration ==
  
−
{| class="wikitable"  
+
{| class="wikitable"
 
! latexfontsize="scriptsize" | Pin  
 
! latexfontsize="scriptsize" | Pin  
 
! latexfontsize="scriptsize" | Pin Name
 
! latexfontsize="scriptsize" | Pin Name
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
+
! latexfontsize="scriptsize" |Voltage domain
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
−
! latexfontsize="scriptsize" | Alternative Functions
+
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
 
|J1.1
 
|J1.1
Line 86: Line 116:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 97: Line 128:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 106: Line 138:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 115: Line 148:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 124: Line 158:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 133: Line 168:
 
| -
 
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 142: Line 178:
 
|NVCC_1V8
 
|NVCC_1V8
 
|I/O
 
|I/O
−
|must be level translated if used @ 3V3
+
|Must be level translated if used @ 3V3
 +
Internally pulled-up to 1.8V during bootstrap
 +
|
 
|
 
|
 
|-
 
|-
Line 151: Line 189:
 
|NVCC_1V8
 
|NVCC_1V8
 
|I/O
 
|I/O
−
|must be level translated if used @ 3V3
+
|Must be level translated if used @ 3V3
 +
Internally pulled-up to 1.8V during bootstrap
 +
|
 
|
 
|
 
|-
 
|-
Line 160: Line 200:
 
| -
 
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 169: Line 210:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 178: Line 220:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 187: Line 230:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 196: Line 240:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 205: Line 250:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 214: Line 260:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 223: Line 270:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 232: Line 280:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 241: Line 290:
 
| -
 
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.37
+
| rowspan="4" |J1.37
 +
| rowspan="4" |GPIO1_IO00
 +
| rowspan="4" |CPU.GPIO1_IO00
 +
| rowspan="4" |T6
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 
|GPIO1_IO00
 
|GPIO1_IO00
−
|CPU.GPIO1_IO00
 
−
|T6
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.39
+
|ALT1
 +
|CCM_ENET_PHY_REF_CLK_ROOT
 +
|-
 +
|ALT5
 +
|ANAMIX_REF_CLK_32K
 +
|-
 +
|ALT6
 +
|CCM_EXT_CLK1
 +
|-
 +
| rowspan="4" |J1.39
 +
| rowspan="4" |GPIO1_IO01
 +
| rowspan="4" |CPU.GPIO1_IO01
 +
| rowspan="4" |T7
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |Internally used for ETH PHY reset, do not connect
 +
|ALT0
 
|GPIO1_IO01
 
|GPIO1_IO01
−
|CPU.GPIO1_IO01
 
−
|T7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.41
+
|ALT1
−
|SPDIF_EXT_CLK
+
|PWM1_OUT
−
|CPU.SPDIF_EXT_CLK
+
|-
−
|E6
+
|ALT5
−
|NVCC_3V3
+
|ANAMIX_REF_CLK_25M
−
|I/O
+
|-
−
|
+
|ALT6
−
|
+
|CCM_EXT_CLK2
 +
|-
 +
| rowspan="3" |J1.41
 +
| rowspan="3" |SPDIF_EXT_CLK
 +
| rowspan="3" |CPU.SPDIF_EXT_CLK
 +
| rowspan="3" |E6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SPDIF1_EXT_CLK
 +
|-
 +
|ALT1
 +
|PWM1_OUT
 +
|-
 +
|ALT5
 +
|GPIO5_IO05
 
|-
 
|-
−
|J1.43
+
| rowspan="3" |J1.43
 +
| rowspan="3" |GPIO1_IO13
 +
| rowspan="3" |CPU.GPIO1_IO13
 +
| rowspan="3" |K6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |Internally used, do not connect
 +
|ALT0
 
|GPIO1_IO13
 
|GPIO1_IO13
−
|CPU.GPIO1_IO13
+
|-
−
|K6
+
|ALT1
−
|NVCC_3V3
+
|USB1_OTG_OC
−
|I/O
+
|-
−
|
+
|ALT5
−
|
+
|PWM2_OUT
 
|-
 
|-
 
|J1.45
 
|J1.45
 
|VDD_PHY_1V8
 
|VDD_PHY_1V8
 +
|
 
|
 
|
 
|
 
|
Line 289: Line 374:
 
|
 
|
 
|-
 
|-
−
|J1.47
+
| rowspan="3" |J1.47
 +
| rowspan="3" |ECSPI2_SCLK
 +
| rowspan="3" |CPU.ECSPI2_SCLK
 +
| rowspan="3" |C5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI2_SCLK
 
|ECSPI2_SCLK
−
|CPU.ECSPI2_SCLK
 
−
|C5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.49
+
|ALT1
 +
|UART4_RX
 +
|-
 +
|ALT5
 +
|GPIO5_IO10
 +
|-
 +
| rowspan="3" |J1.49
 +
| rowspan="3" |ECSPI2_MOSI
 +
| rowspan="3" |CPU.ECSPI2_MOSI
 +
| rowspan="3" |E5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI2_MOSI
 
|ECSPI2_MOSI
−
|CPU.ECSPI2_MOSI
 
−
|E5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.51
+
|ALT1
 +
|UART4_TX
 +
|-
 +
|ALT5
 +
|GPIO5_IO11
 +
|-
 +
| rowspan="3" |J1.51
 +
| rowspan="3" |GPIO1_IO08
 +
| rowspan="3" |CPU.GPIO1_IO08
 +
| rowspan="3" |N7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|GPIO1_IO08
 
|GPIO1_IO08
−
|CPU.GPIO1_IO08
 
−
|N7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.53
+
|ALT1
 +
|ENET1_1588_EVENT0_IN
 +
|-
 +
|ALT5
 +
|USDHC2_RESET_B
 +
|-
 +
| rowspan="3" |J1.53
 +
| rowspan="3" |GPIO1_IO09
 +
| rowspan="3" |CPU.GPIO1_IO09
 +
| rowspan="3" |M7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|GPIO1_IO09
 
|GPIO1_IO09
−
|CPU.GPIO1_IO09
 
−
|M7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.55
+
|ALT1
 +
|ENET1_1588_EVENT0_OUT
 +
|-
 +
|ALT5
 +
|SDMA2_EXT_EVENT0
 +
|-
 +
| rowspan="3" |J1.55
 +
| rowspan="3" |ECSPI2_MISO
 +
| rowspan="3" |CPU.ECSPI2_MISO
 +
| rowspan="3" |B5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI2_MISO
 
|ECSPI2_MISO
−
|CPU.ECSPI2_MISO
+
|-
−
|B5
+
|ALT1
−
|NVCC_3V3
+
|UART4_CTS_B
−
|I/O
+
|-
−
|
+
|ALT5
−
|
+
|GPIO5_IO12
 
|-
 
|-
 
|J1.57
 
|J1.57
Line 338: Line 458:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.59
+
| rowspan="3" |J1.59
 +
| rowspan="3" |ECSPI2_SS0
 +
| rowspan="3" |CPU.ECSPI2_SS0
 +
| rowspan="3" |A5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI2_SS0
 
|ECSPI2_SS0
−
|CPU.ECSPI2_SS0
 
−
|A5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.61
+
|ALT1
 +
|UART4_RTS_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO13
 +
|-
 +
| rowspan="3" |J1.61
 +
| rowspan="3" |GPIO1_IO05
 +
| rowspan="3" |CPU.GPIO1_IO05
 +
| rowspan="3" |P7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connect
 +
Pulled-up to NVCC_3V3
 +
|ALT0
 
|GPIO1_IO05
 
|GPIO1_IO05
−
|CPU.GPIO1_IO05
 
−
|P7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.63
+
|ALT1
 +
|M4_NMI
 +
|-
 +
|ALT5
 +
|CCM_PMIC_READY
 +
|-
 +
| rowspan="3" |J1.63
 +
| rowspan="3" |I2C2_SCL
 +
| rowspan="3" |CPU.I2C2_SCL
 +
| rowspan="3" |G7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|I2C2_SCL
 
|I2C2_SCL
−
|CPU.I2C2_SCL
 
−
|G7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.65
+
|ALT1
 +
|ENET1_1588_EVENT1_IN
 +
|-
 +
|ALT5
 +
|GPIO5_IO16
 +
|-
 +
| rowspan="3" |J1.65
 +
| rowspan="3" |I2C2_SDA
 +
| rowspan="3" |CPU.I2C2_SDA
 +
| rowspan="3" |F7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|I2C2_SDA
 
|I2C2_SDA
−
|CPU.I2C2_SDA
 
−
|F7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.67
+
|ALT1
 +
|ENET1_1588_EVENT1_OUT
 +
|-
 +
|ALT5
 +
|GPIO5_IO17
 +
|-
 +
| rowspan="4" |J1.67
 +
| rowspan="4" |GPIO1_IO06
 +
| rowspan="4" |CPU.GPIO1_IO06
 +
| rowspan="4" |N5
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
 +
|ALT0
 
|GPIO1_IO06
 
|GPIO1_IO06
−
|CPU.GPIO1_IO06
 
−
|N5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.69
+
|ALT1
−
|SAI2_RXC
+
|ENET1_MDC
−
|CPU.SAI2_RXC
+
|-
−
|H3
+
|ALT5
−
|NVCC_3V3
+
|USDHC1_CD_B
−
|I/O
+
|-
−
|
+
|ALT6
−
|
+
|CCM_EXT_CLK3
 +
|-
 +
| rowspan="3" |J1.69
 +
| rowspan="3" |SAI2_RXC
 +
| rowspan="3" |CPU.SAI2_RXC
 +
| rowspan="3" |H3
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_RX_BCLK
 +
|-
 +
|ALT1
 +
|SAI5_TX_BCLK
 +
|-
 +
|ALT5
 +
|GPIO4_IO22
 +
|-
 +
| rowspan="3" |J1.71
 +
| rowspan="3" |SAI2_RXFS
 +
| rowspan="3" |CPU.SAI2_RXFS
 +
| rowspan="3" |J4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_RX_SYNC
 +
|-
 +
|ALT1
 +
|SAI5_TX_SYNC
 
|-
 
|-
−
|J1.71
+
|ALT5
−
|SAI2_RXFS
+
|GPIO4_IO21
−
|CPU.SAI2_RXFS
 
−
|J4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
 
|J1.73
 
|J1.73
Line 410: Line 584:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 
|
 
|
−
|
 
−
|-
 
−
|J1.75
 
−
|SD2_DATA0
 
−
|CPU.SD2_DATA0
 
−
|N22
 
−
|NVCC_3V3
 
−
|I/O
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.77
+
| rowspan="2" |J1.75
−
|SD2_DATA1
+
| rowspan="2" |SD2_DATA0
−
|CPU.SD2_DATA1
+
| rowspan="2" |CPU.SD2_DATA0
−
|N21
+
| rowspan="2" |N22
−
|NVCC_3V3
+
| rowspan="2" |NVCC_3V3
−
|I/O
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
−
|
+
|ALT0
 +
|USDHC2_DATA0
 
|-
 
|-
−
|J1.79
+
|ALT5
−
|SD2_DATA2
+
|GPIO2_IO15
−
|CPU.SD2_DATA2
+
|-
−
|P22
+
| rowspan="2" |J1.77
−
|NVCC_3V3
+
| rowspan="2" |SD2_DATA1
−
|I/O
+
| rowspan="2" |CPU.SD2_DATA1
−
|
+
| rowspan="2" |N21
−
|
+
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_DATA1
 +
|-
 +
|ALT5
 +
|GPIO2_IO16
 +
|-
 +
| rowspan="2" |J1.79
 +
| rowspan="2" |SD2_DATA2
 +
| rowspan="2" |CPU.SD2_DATA2
 +
| rowspan="2" |P22
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_DATA2
 +
|-
 +
|ALT5
 +
|GPIO2_IO17
 +
|-
 +
| rowspan="2" |J1.81
 +
| rowspan="2" |SD2_DATA3
 +
| rowspan="2" |CPU.SD2_DATA03
 +
| rowspan="2" |P21
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_DATA3
 +
|-
 +
|ALT5
 +
|GPIO2_IO18
 +
|-
 +
| rowspan="2" |J1.83
 +
| rowspan="2" |SD2_CMD
 +
| rowspan="2" |CPU.SD2_CMD
 +
| rowspan="2" |M22
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_CMD
 
|-
 
|-
−
|J1.81
+
|ALT5
−
|SD2_DATA3
+
|GPIO2_IO14
−
|CPU.SD2_DATA03
 
−
|P21
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.83
+
| rowspan="2" |J1.85
−
|SD2_CMD
+
| rowspan="2" |SD2_CLK
−
|CPU.SD2_CMD
+
| rowspan="2" |CPU.SD2_CLK
−
|M22
+
| rowspan="2" |L22
−
|NVCC_3V3
+
| rowspan="2" |NVCC_3V3
−
|I/O
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
−
|
+
|ALT0
 +
|USDHC2_CLK
 
|-
 
|-
−
|J1.85
+
|ALT5
−
|SD2_CLK
+
|GPIO2_IO13
−
|CPU.SD2_CLK
 
−
|L22
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
 
|J1.87
 
|J1.87
Line 473: Line 672:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 
|
 
|
−
|
 
−
|-
 
−
|J1.89
 
−
|UART3_TXD
 
−
|CPU.UART3_TXD
 
−
|B7
 
−
|NVCC_3V3
 
−
|I/O
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.91
+
| rowspan="3" |J1.89
−
|UART3_RXD
+
| rowspan="3" |UART3_TXD
−
|CPU.UART3_RXD
+
| rowspan="3" |CPU.UART3_TXD
−
|A6
+
| rowspan="3" |B7
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I/O
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|UART3_TX
 +
|-
 +
|ALT1
 +
|UART1_RTS_B
 
|-
 
|-
−
|J1.93
+
|ALT5
−
|UART4_TXD
+
|GPIO5_IO27
−
|CPU.UART4_TXD
 
−
|D7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.95
+
| rowspan="3" |J1.91
−
|UART4_RXD
+
| rowspan="3" |UART3_RXD
−
|CPU.UART4_RXD
+
| rowspan="3" |CPU.UART3_RXD
−
|C6
+
| rowspan="3" |A6
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I/O
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|UART3_RX
 
|-
 
|-
−
|J1.97
+
|ALT1
−
|SD2_WP
+
|UART1_CTS_B
−
|CPU.SD2_WP
 
−
|M21
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.99
+
|ALT5
−
|SD2_RST_B
+
|GPIO5_IO26
−
|CPU.SD2_RESET_B
 
−
|R22
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.101
+
| rowspan="4" |J1.93
−
|HDMI_DDC_SCL
+
| rowspan="4" |UART4_TXD
−
|CPU.HDMI_DDC_SCL
+
| rowspan="4" |CPU.UART4_TXD
−
|R3
+
| rowspan="4" |D7
−
|VDD_PHY_1V8
+
| rowspan="4" |NVCC_3V3
−
|I/O
+
| rowspan="4" |I/O
−
|
+
| rowspan="4" |
−
|
+
|ALT0
 +
|UART4_TX
 +
|-
 +
|ALT1
 +
|UART2_RTS_B
 +
|-
 +
|ALT2
 +
|PCIE2_CLKREQ_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO29
 +
|-
 +
| rowspan="4" |J1.95
 +
| rowspan="4" |UART4_RXD
 +
| rowspan="4" |CPU.UART4_RXD
 +
| rowspan="4" |C6
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|UART4_RX
 +
|-
 +
|ALT1
 +
|UART2_CTS_B
 +
|-
 +
|ALT2
 +
|PCIE1_CLKREQ_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO28
 +
|-
 +
| rowspan="2" |J1.97
 +
| rowspan="2" |SD2_WP
 +
| rowspan="2" |CPU.SD2_WP
 +
| rowspan="2" |M21
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_WP
 +
|-
 +
|ALT5
 +
|GPIO2_IO20
 +
|-
 +
| rowspan="2" |J1.99
 +
| rowspan="2" |SD2_RST_B
 +
| rowspan="2" |CPU.SD2_RESET_B
 +
| rowspan="2" |R22
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_RESET_B
 +
|-
 +
|ALT5
 +
|GPIO2_IO19
 +
|-
 +
|J1.101
 +
|HDMI_DDC_SCL
 +
|CPU.HDMI_DDC_SCL
 +
|R3
 +
|VDD_PHY_1V8
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
 
|J1.103
 
|J1.103
Line 547: Line 790:
 
|VDD_PHY_1V8
 
|VDD_PHY_1V8
 
|I/O
 
|I/O
 +
|
 
|
 
|
 
|
 
|
Line 557: Line 801:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 566: Line 811:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 572: Line 818:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 584: Line 831:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 593: Line 841:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 602: Line 851:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 611: Line 861:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 620: Line 871:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 629: Line 881:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 638: Line 891:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 647: Line 901:
 
|D
 
|D
 
|connected with capacitor in series
 
|connected with capacitor in series
 +
|
 
|
 
|
 
|-
 
|-
Line 655: Line 910:
 
|VDD_PHY_1V8
 
|VDD_PHY_1V8
 
|I/O
 
|I/O
 +
|
 
|
 
|
 
|
 
|
Line 664: Line 920:
 
|VDD_PHY_1V8
 
|VDD_PHY_1V8
 
|I/O
 
|I/O
 +
|
 
|
 
|
 
|
 
|
Line 671: Line 928:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 682: Line 940:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 691: Line 950:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 700: Line 960:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 709: Line 970:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 718: Line 980:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 727: Line 990:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 736: Line 1,000:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 745: Line 1,010:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 754: Line 1,020:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 763: Line 1,030:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 770: Line 1,038:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 781: Line 1,050:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 790: Line 1,060:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 799: Line 1,070:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 808: Line 1,080:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 817: Line 1,090:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 826: Line 1,100:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 835: Line 1,110:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 844: Line 1,120:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 853: Line 1,130:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 862: Line 1,140:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 869: Line 1,148:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
| rowspan="2" |J1.177
 +
| rowspan="2" |SD2_CD_B
 +
| rowspan="2" |CPU.SD2_CD_B
 +
| rowspan="2" |L21
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC2_CD_B
 
|-
 
|-
−
|J1.177
+
|ALT5
−
|SD2_CD_B
+
|GPIO2_IO12
−
|CPU.SD2_CD_B
 
−
|L21
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.179
+
| rowspan="3" |J1.179
 +
| rowspan="3" |ECSPI1_SS0
 +
| rowspan="3" |CPU.ECSPI1_SS0
 +
| rowspan="3" |D4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI1_SS0
 
|ECSPI1_SS0
−
|CPU.ECSPI1_SS0
 
−
|D4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.181
+
|ALT1
 +
|UART3_RTS_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO09
 +
|-
 +
| rowspan="3" |J1.181
 +
| rowspan="3" |ECSPI1_SCLK
 +
| rowspan="3" |CPU.ECSPI1_SCLK
 +
| rowspan="3" |D5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI1_SCLK
 
|ECSPI1_SCLK
−
|CPU.ECSPI1_SCLK
 
−
|D5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.183
+
|ALT1
 +
|UART3_RX
 +
|-
 +
|ALT5
 +
|GPIO5_IO06
 +
|-
 +
| rowspan="3" |J1.183
 +
| rowspan="3" |ECSPI1_MISO
 +
| rowspan="3" |CPU.ECSPI1_MISO
 +
| rowspan="3" |B4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|ECSPI1_MISO
 
|ECSPI1_MISO
−
|CPU.ECSPI1_MISO
 
−
|B4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.185
+
|ALT1
 +
|UART3_CTS_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO08
 +
|-
 +
| rowspan="3" |J1.185
 +
| rowspan="3" |GPIO1_IO03
 +
| rowspan="3" |CPU.GPIO1_IO03
 +
| rowspan="3" |P4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|GPIO1_IO03
 
|GPIO1_IO03
−
|CPU.GPIO1_IO03
 
−
|P4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.187
+
|ALT1
−
|UART1_TXD
+
|USDHC1_VSELECT
−
|???
+
|-
−
|
+
|ALT5
−
|NVCC_3V3
+
|SDMA1_EXT_EVENT0
−
|I/O
+
|-
−
|
+
| rowspan="3" |J1.187
−
|
+
| rowspan="3" |UART2_TXD
 +
| rowspan="3" |CPU.UART2_TXD
 +
| rowspan="3" |D6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |used as default Linux console
 +
|ALT0
 +
|UART2_TX
 
|-
 
|-
−
|J1.189
+
|ALT1
−
|UART1_RXD
+
|ECSPI3_SS0
−
|???
 
−
|
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.191
+
|ALT5
−
|UART2_TXD
+
|GPIO5_IO25
−
|???
 
−
|
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.193
+
| rowspan="3" |J1.189
 +
| rowspan="3" |UART2_RXD
 +
| rowspan="3" |CPU.UART2_RXD
 +
| rowspan="3" |B6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |used as default Linux console
 +
|ALT0
 
|UART2_RXD
 
|UART2_RXD
−
|???
 
−
|
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.195
+
|ALT1
−
|ECSPI1_MOSI
+
|ECSPI3_MISO
−
|CPU.ECSPI1_MOSI
+
|-
−
|A4
+
|ALT5
−
|NVCC_3V3
+
|GPIO5_IO24
−
|I/O
+
|-
−
|
+
| rowspan="3" |J1.191
−
|
+
| rowspan="3" |UART1_TXD
 +
| rowspan="3" |CPU.UART1_TXD
 +
| rowspan="3" |A7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|UART1_TX
 +
|-
 +
|ALT1
 +
|ECSPI3_MOSI
 +
|-
 +
|ALT5
 +
|GPIO5_IO23
 +
|-
 +
| rowspan="3" |J1.193
 +
| rowspan="3" |UART1_RXD
 +
| rowspan="3" |CPU.UART1_RXD
 +
| rowspan="3" |C7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|UART1_RXD
 +
|-
 +
|ALT1
 +
|ECSPI3_SCLK
 +
|-
 +
|ALT5
 +
|GPIO5_IO22
 +
|-
 +
| rowspan="3" |J1.195
 +
| rowspan="3" |ECSPI1_MOSI
 +
| rowspan="3" |CPU.ECSPI1_MOSI
 +
| rowspan="3" |A4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|ECSPI1_MOSI
 +
|-
 +
|ALT1
 +
|UART3_TX
 +
|-
 +
|ALT5
 +
|GPIO5_IO07
 
|-
 
|-
−
|J1.197
+
| rowspan="4" |J1.197
 +
| rowspan="4" |GPIO1_IO14
 +
| rowspan="4" |CPU.GPIO1_IO14
 +
| rowspan="4" |K7
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 
|GPIO1_IO14
 
|GPIO1_IO14
−
|CPU.GPIO1_IO14
 
−
|K7
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.199
+
|ALT1
 +
|USB2_OTG_PWR
 +
|-
 +
|ALT5
 +
|PWM3_OUT
 +
|-
 +
|ALT6
 +
|CCM_CLKO1
 +
|-
 +
| rowspan="3" |J1.199
 +
| rowspan="3" |GPIO1_IO04
 +
| rowspan="3" |CPU.GPIO1_IO04
 +
| rowspan="3" |P5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|GPIO1_IO04
 
|GPIO1_IO04
−
|CPU.GPIO1_IO04
 
−
|P5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.201
+
|ALT1
 +
|USDHC2_VSELECT
 +
|-
 +
|ALT5
 +
|SDMA1_EXT_EVENT1
 +
|-
 +
| rowspan="3" |J1.201
 +
| rowspan="3" |GPIO1_IO12
 +
| rowspan="3" |CPU.GPIO1_IO12
 +
| rowspan="3" |L7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|GPIO1_IO12
 
|GPIO1_IO12
−
|CPU.GPIO1_IO12
+
|-
−
|L7
+
|ALT1
−
|NVCC_3V3
+
|USB1_OTG_PWR
−
|I/O
+
|-
−
|
+
|ALT5
−
|
+
|SDMA2_EXT_EVENT1
 
|-
 
|-
 
|J1.203
 
|J1.203
Line 995: Line 1,366:
 
|DGND
 
|DGND
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
| -
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,002: Line 1,374:
 
|}
 
|}
  
−
===Pinout Table EVEN  pins declaration ===
+
==SODIMM J1 EVEN  pins declaration ==
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 1,009: Line 1,381:
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
+
! latexfontsize="scriptsize" | Voltage domain  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
−
! latexfontsize="scriptsize" | Alternative Functions
+
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
 
|J1.2
 
|J1.2
Line 1,020: Line 1,392:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,029: Line 1,402:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 1,038: Line 1,412:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 1,047: Line 1,422:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 1,056: Line 1,432:
 
|3.3VIN
 
|3.3VIN
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 1,065: Line 1,442:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,074: Line 1,452:
 
| -
 
| -
 
|S
 
|S
 +
|
 
|
 
|
 
|
 
|
Line 1,084: Line 1,463:
 
|I
 
|I
 
|internal pull-up 100k to NVCC_SNVS
 
|internal pull-up 100k to NVCC_SNVS
 +
|
 
|
 
|
 
|-
 
|-
Line 1,092: Line 1,472:
 
|NVCC_3V3
 
|NVCC_3V3
 
|O
 
|O
 +
|
 
|
 
|
 
|
 
|
Line 1,102: Line 1,483:
 
|I
 
|I
 
|internal pull-up to NVCC_3V3
 
|internal pull-up to NVCC_3V3
 +
|
 
|
 
|
 
|-
 
|-
Line 1,113: Line 1,495:
 
|I/O
 
|I/O
 
|internal pull-up 100k to NVCC_SNVS
 
|internal pull-up 100k to NVCC_SNVS
 +
|
 
|
 
|
 
|-
 
|-
Line 1,123: Line 1,506:
 
|internal pull-up to NVCC_SNVS
 
|internal pull-up to NVCC_SNVS
 
|
 
|
 +
|
 +
|-
 +
| rowspan="4" |J1.26
 +
| rowspan="4" |SAI3_RXC
 +
| rowspan="4" |CPU.SAI3_RXC
 +
| rowspan="4" |F4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_RX_BCLK
 +
|-
 +
|ALT1
 +
|GPT1_CAPTURE2
 +
|-
 +
|ALT2
 +
|SAI5_RX_BCLK
 
|-
 
|-
−
|J1.26
+
|ALT5
−
|SAI3_RXC
+
|GPIO4_IO29
−
|CPU.SAI3_RXC
 
−
|F4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.28
+
| rowspan="4" |J1.28
 +
| rowspan="4" |GPIO1_IO02
 +
| rowspan="4" |CPU.GPIO1_IO02
 +
| rowspan="4" |R4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |Internally used for SW reset, do not connect
 +
|ALT0
 
|GPIO1_IO02
 
|GPIO1_IO02
−
|CPU.GPIO1_IO02
+
|-
−
|R4
+
|ALT1
−
|NVCC_3V3
+
|WDOG1_WDOG_B
−
|I/O
+
|-
−
|
+
|ALT5
−
|
+
|WDOG1_WDOG_ANY
 +
|-
 +
|ALT7
 +
|SJC_DE_B
 
|-
 
|-
 
|J1.30
 
|J1.30
Line 1,150: Line 1,554:
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
| rowspan="4" |J1.32
 +
| rowspan="4" |SAI3_RXD
 +
| rowspan="4" |CPU.SAI3_RXD
 +
| rowspan="4" |F3
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_RX_DATA0
 +
|-
 +
|ALT1
 +
|GPT1_COMPARE1
 +
|-
 +
|ALT2
 +
|SAI5_RX_DATA0
 
|-
 
|-
−
|J1.32
+
|ALT5
−
|SAI3_RXD
+
|GPIO4_IO30
−
|CPU.SAI3_RXD
 
−
|F3
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.34
+
| rowspan="3" |J1.34
 +
| rowspan="3" |SAI2_MCLK
 +
| rowspan="3" |CPU.SAI2_MCLK
 +
| rowspan="3" |H5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 
|SAI2_MCLK
 
|SAI2_MCLK
−
|CPU.SAI2_MCLK
 
−
|H5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.36
+
|ALT1
−
|SAI3_RXFS
+
|SAI5_MCLK
−
|CPU.SAI3_RXFS
+
|-
−
|G4
+
|ALT5
−
|NVCC_3V3
+
|GPIO4_IO27
−
|I/O
+
|-
−
|
+
| rowspan="4" |J1.36
−
|
+
| rowspan="4" |SAI3_RXFS
 +
| rowspan="4" |CPU.SAI3_RXFS
 +
| rowspan="4" |G4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_RX_SYNC
 +
|-
 +
|ALT1
 +
|GPT1_CAPTURE1
 +
|-
 +
|ALT2
 +
|SAI5_RX_SYNC
 +
|-
 +
|ALT5
 +
|GPIO4_IO28
 
|-
 
|-
−
|J1.38
+
| rowspan="4" |J1.38
 +
| rowspan="4" |I2C3_SCL
 +
| rowspan="4" |CPU.I2C3_SCL
 +
| rowspan="4" |G8
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 
|I2C3_SCL
 
|I2C3_SCL
−
|CPU.I2C3_SCL
 
−
|G8
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.40
+
|ALT1
−
|SAI3_TXFS
+
|PWM4_OUT
−
|CPU.SAI3_TXFS
+
|-
−
|G3
+
|ALT2
−
|NVCC_3V3
+
|GPT2_CLK
−
|I/O
+
|-
−
|
+
|ALT5
−
|
+
|GPIO5_IO18
 
|-
 
|-
−
|J1.42
+
| rowspan="4" |J1.40
−
|SPDIF_RX
+
| rowspan="4" |SAI3_TXFS
−
|CPU.SPDIF_RX
+
| rowspan="4" |CPU.SAI3_TXFS
−
|G6
+
| rowspan="4" |G3
−
|NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
|I/O
+
| rowspan="4" |I/O
−
|
+
| rowspan="4" |
−
|
+
|ALT0
 +
|SAI3_TX_SYNC
 
|-
 
|-
−
|J1.44
+
|ALT1
−
|SPDIF_TX
+
|GPT1_CLK
−
|CPU.SPDIF_TX
 
−
|F6
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.46
+
|ALT2
−
|SAI3_MCLK
+
|SAI5_RX_DATA1
−
|CPU.SAI3_MCLK
 
−
|D3
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.48
+
|ALT5
−
|I2C3_SDA
+
|GPIO4_IO31
−
|CPU.I2C3_SDA
 
−
|E9
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.50
+
| rowspan="3" |J1.42
−
|SAI3_TXC
+
| rowspan="3" |SPDIF_RX
−
|CPU.SAI3_TXC
+
| rowspan="3" |CPU.SPDIF_RX
−
|C4
+
| rowspan="3" |G6
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I/O
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|SPDIF1_IN
 
|-
 
|-
−
|J1.52
+
|ALT1
−
|SAI3_TXD
+
|PWM2_OUT
−
|CPU.SAI3_TXD
+
|-
−
|C3
+
|ALT5
−
|NVCC_3V3
+
|GPIO5_IO04
−
|I/O
+
|-
−
|
+
| rowspan="3" |J1.44
−
|
+
| rowspan="3" |SPDIF_TX
 +
| rowspan="3" |CPU.SPDIF_TX
 +
| rowspan="3" |F6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SPDIF1_OUT
 +
|-
 +
|ALT1
 +
|PWM3_OUT
 +
|-
 +
|ALT5
 +
|GPIO5_IO03
 +
|-
 +
| rowspan="4" |J1.46
 +
| rowspan="4" |SAI3_MCLK
 +
| rowspan="4" |CPU.SAI3_MCLK
 +
| rowspan="4" |D3
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_MCLK
 +
|-
 +
|ALT1
 +
|PWM4_OUT
 +
|-
 +
|ALT2
 +
|SAI5_MCLK
 +
|-
 +
|ALT5
 +
|GPIO5_IO02
 +
|-
 +
| rowspan="4" |J1.48
 +
| rowspan="4" |I2C3_SDA
 +
| rowspan="4" |CPU.I2C3_SDA
 +
| rowspan="4" |E9
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|I2C3_SDA
 +
|-
 +
|ALT1
 +
|PWM3_OUT
 +
|-
 +
|ALT2
 +
|GPT3_CLK
 +
|-
 +
|ALT5
 +
|GPIO5_IO19
 +
|-
 +
| rowspan="4" |J1.50
 +
| rowspan="4" |SAI3_TXC
 +
| rowspan="4" |CPU.SAI3_TXC
 +
| rowspan="4" |C4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_TX_BCLK
 +
|-
 +
|ALT1
 +
|GPT1_COMPARE2
 +
|-
 +
|ALT2
 +
|SAI5_RX_DATA2
 +
|-
 +
|ALT5
 +
|GPIO5_IO00
 +
|-
 +
| rowspan="4" |J1.52
 +
| rowspan="4" |SAI3_TXD
 +
| rowspan="4" |CPU.SAI3_TXD
 +
| rowspan="4" |C3
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_TX_DATA0
 +
|-
 +
|ALT1
 +
|GPT1_COMPARE3
 +
|-
 +
|ALT2
 +
|SAI5_RX_DATA3
 +
|-
 +
|ALT5
 +
|GPIO5_IO01
 +
|-
 +
| rowspan="2" |J1.54
 +
| rowspan="2" |GPIO1_IO10
 +
| rowspan="2" |CPU.GPIO1_IO10
 +
| rowspan="2" |M7
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
 +
|ALT0
 +
|GPIO1_IO10
 
|-
 
|-
−
|J1.54
+
|ALT1
−
|SD1_STROBE
+
|USB1_OTG_ID
−
|CPU.SD1_STROBE
 
−
|T24
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|internally used for eMMC
 
−
|
 
 
|-
 
|-
 
|J1.56
 
|J1.56
Line 1,265: Line 1,775:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.58
+
| rowspan="4" |J1.58
 +
| rowspan="4" |SAI5_MCLK
 +
| rowspan="4" |CPU.SAI5_MCLK
 +
| rowspan="4" |K4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 
|SAI5_MCLK
 
|SAI5_MCLK
−
|CPU.SAI5_MCLK
 
−
|K4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.60
+
|ALT1
 +
|SAI1_TX_BCLK
 +
|-
 +
|ALT2
 +
|SAI4_MCLK
 +
|-
 +
|ALT5
 +
|GPIO3_IO25
 +
|-
 +
| rowspan="4" |J1.60
 +
| rowspan="4" |GPIO1_IO15
 +
| rowspan="4" |CPU.GPIO1_IO15
 +
| rowspan="4" |J6
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 
|GPIO1_IO15
 
|GPIO1_IO15
−
|CPU.GPIO1_IO15
 
−
|J6
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.62
+
|ALT1
−
|SAI5_RXFS
+
|USB2_OTG_OC
−
|CPU.SAI5_RXFS
+
|-
−
|N4
+
|ALT5
−
|NVCC_3V3
+
|PWM4_OUT
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.64
+
|ALT6
−
|SAI5_RXC
+
|CCM_CLKO2
−
|CPU.SAI5_RXC
 
−
|L5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.66
+
| rowspan="3" |J1.62
−
|SAI2_TXC
+
| rowspan="3" |SAI5_RXFS
−
|CPU.SAI2_TXC
+
| rowspan="3" |CPU.SAI5_RXFS
−
|J5
+
| rowspan="3" |N4
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I/O
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|SAI5_RX_SYNC
 
|-
 
|-
−
|J1.68
+
|ALT1
−
|SAI2_TXD0
+
|SAI1_TX_DATA0
−
|CPU.SAI2_TXD0
 
−
|G5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.70
+
|ALT5
−
|SAI2_TXFS
+
|GPIO3_IO19
−
|CPU.SAI2_TXFS
+
|-
−
|H4
+
| rowspan="3" |J1.64
−
|NVCC_3V3
+
| rowspan="3" |SAI5_RXC
−
|I/O
+
| rowspan="3" |CPU.SAI5_RXC
−
|
+
| rowspan="3" |L5
−
|
+
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI5_RX_BCLK
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA1
 +
|-
 +
|ALT5
 +
|GPIO3_IO20
 +
|-
 +
| rowspan="3" |J1.66
 +
| rowspan="3" |SAI2_TXC
 +
| rowspan="3" |CPU.SAI2_TXC
 +
| rowspan="3" |J5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_TX_BCLK
 
|-
 
|-
−
|J1.72
+
|ALT1
−
|SAI2_RXD0
+
|SAI5_TX_DATA2
−
|CPU.SAI2_RXD0
 
−
|H6
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.74
+
|ALT5
−
|SAI5_RXD0
+
|GPIO4_IO25
−
|CPU.SAI5_RXD0
 
−
|M5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.76
+
| rowspan="3" |J1.68
−
|SAI5_RXD1
+
| rowspan="3" |SAI2_TXD0
−
|CPU.SAI5_RXD1
+
| rowspan="3" |CPU.SAI2_TXD0
−
|L4
+
| rowspan="3" |G5
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I/O
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|SAI2_TX_DATA0
 
|-
 
|-
−
|J1.78
+
|ALT1
−
|SAI5_RXD2
+
|SAI5_TX_DATA3
−
|CPU.SAI5_RXD2
 
−
|M4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.80
+
|ALT5
−
|SAI5_RXD3
+
|GPIO4_IO26
−
|CPU.SAI5_RXD3
 
−
|K5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.82
+
| rowspan="3" |J1.70
−
|DGND
+
| rowspan="3" |SAI2_TXFS
−
|DGND
+
| rowspan="3" |CPU.SAI2_TXFS
 +
| rowspan="3" |H4
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_TX_SYNC
 +
|-
 +
|ALT1
 +
|SAI5_TX_DATA1
 +
|-
 +
|ALT5
 +
|GPIO4_IO24
 +
|-
 +
| rowspan="3" |J1.72
 +
| rowspan="3" |SAI2_RXD0
 +
| rowspan="3" |CPU.SAI2_RXD0
 +
| rowspan="3" |H6
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_RX_DATA0
 +
|-
 +
|ALT1
 +
|SAI5_TX_DATA0
 +
|-
 +
|ALT5
 +
|GPIO4_IO23
 +
|-
 +
| rowspan="3" |J1.74
 +
| rowspan="3" |SAI5_RXD0
 +
| rowspan="3" |CPU.SAI5_RXD0
 +
| rowspan="3" |M5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI5_RX_DATA0
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA2
 +
|-
 +
|ALT5
 +
|GPIO3_IO21
 +
|-
 +
| rowspan="5" |J1.76
 +
| rowspan="5" |SAI5_RXD1
 +
| rowspan="5" |CPU.SAI5_RXD1
 +
| rowspan="5" |L4
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |
 +
|ALT0
 +
|SAI5_RX_DATA1
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA3
 +
|-
 +
|ALT2
 +
|SAI1_TX_SYNC
 +
|-
 +
|ALT3
 +
|SAI5_TX_SYNC
 +
|-
 +
|ALT5
 +
|GPIO3_IO212
 +
|-
 +
| rowspan="5" |J1.78
 +
| rowspan="5" |SAI5_RXD2
 +
| rowspan="5" |CPU.SAI5_RXD2
 +
| rowspan="5" |M4
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |
 +
|ALT0
 +
|SAI5_RX_DATA2
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA4
 +
|-
 +
|ALT2
 +
|SAI1_TX_SYNC
 +
|-
 +
|ALT3
 +
|SAI5_TX_BCLK
 +
|-
 +
|ALT5
 +
|GPIO3_IO23
 +
|-
 +
| rowspan="5" |J1.80
 +
| rowspan="5" |SAI5_RXD3
 +
| rowspan="5" |CPU.SAI5_RXD3
 +
| rowspan="5" |K5
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |
 +
|ALT0
 +
|SAI5_RX_DATA3
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA5
 +
|-
 +
|ALT2
 +
|SAI1_TX_SYNC
 +
|-
 +
|ALT3
 +
|SAI5_TX_DATA0
 +
|-
 +
|ALT5
 +
|GPIO3_IO24
 +
|-
 +
|J1.82
 +
|DGND
 +
|DGND
 
| -
 
| -
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,391: Line 2,011:
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
 +
|Internally used for PCIe CLK, do not connect
 
|
 
|
 
|
 
|
Line 1,400: Line 2,021:
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
 +
|Internally used for PCIe CLK, do not connect
 
|
 
|
 
|
 
|
Line 1,409: Line 2,031:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,418: Line 2,041:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,427: Line 2,051:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,436: Line 2,061:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,445: Line 2,071:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,454: Line 2,081:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,463: Line 2,091:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,472: Line 2,101:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,481: Line 2,111:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,490: Line 2,121:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,499: Line 2,131:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,508: Line 2,141:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,517: Line 2,151:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,526: Line 2,161:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,535: Line 2,171:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,544: Line 2,181:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,553: Line 2,191:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,562: Line 2,201:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
 
|J1.124
 
|J1.124
 +
(NAND on board)
 
|NAND_DQS
 
|NAND_DQS
 
|CPU.NAND_DQS
 
|CPU.NAND_DQS
Line 1,571: Line 2,212:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|internally used for NAND
+
|Internally used for NAND, do not connect
 +
|
 
|
 
|
 +
|-
 +
| rowspan="3" |J1.124
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DQS
 +
| rowspan="3" |CPU.NAND_DQS
 +
| rowspan="3" |M20
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DQS
 +
|-
 +
|ALT1
 +
|QSPI_A_DQS
 +
|-
 +
|ALT5
 +
|GPIO3_IO14
 
|-
 
|-
 
|J1.126
 
|J1.126
 +
(NAND on board)
 
|NAND_ALE
 
|NAND_ALE
 
|CPU.NAND_ALE
 
|CPU.NAND_ALE
Line 1,580: Line 2,240:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|internally used for NAND
+
|Internally used for NAND, do not connect
 +
|
 
|
 
|
 
|-
 
|-
−
|J1.128
+
| rowspan="3" |J1.126
−
|NAND_CE0_B  //  SD1_CLK
+
(eMMC on board)
−
|CPU.NAND_CE0_B // CPU.SD1_CLK
+
| rowspan="3" |NAND_ALE
−
|H19  //  L25
+
| rowspan="3" |CPU.NAND_ALE
−
|NVCC_1V8  //  NVCC_3V3 ???
+
| rowspan="3" |G19
−
|I/O
+
| rowspan="3" |NVCC_3V3
−
|???
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_ALE
 
|-
 
|-
−
|J1.130
+
|ALT1
−
|NAND_CE1_B  //  SD1_CMD
+
|QSPI_A_SCLK
−
|CPU.NAND_CE1_B // CPU.SD1_CMD
 
−
|G21  //  L24
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.132
+
|ALT5
−
|NAND_CE2_B  //  SD1_RST_B
+
|GPIO3_IO00
−
|CPU.NAND_CE2_B // CPU.SD1_RST_B
 
−
|F21  //  R24
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.134
+
| rowspan="2" |J1.128
−
|NAND_CE3_B  //  SD1_STROBE
+
(NAND on board)
−
|CPU.NAND_CE3_B // CPU.SD1_STROBE
+
| rowspan="2" |SD1_CLK
−
|H20  //  T24
+
| rowspan="2" |CPU.SD1_CLK
−
|NVCC_1V8 //  NVCC_3V3 ???
+
| rowspan="2" |L25
−
|I/O
+
| rowspan="2" |NVCC_3V3
−
|???
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_CLK
 
|-
 
|-
−
|J1.136
+
|ALT5
 +
|GPIO2_IO00
 +
|-
 +
| rowspan="3" |J1.128
 +
(eMMC on board)
 +
| rowspan="3" |NAND_CE0_B
 +
| rowspan="3" |CPU.NAND_CE0_B
 +
| rowspan="3" |H19
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CE0_B
 +
|-
 +
|ALT1
 +
|QSPI_A_SS0_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO01
 +
|-
 +
| rowspan="2" |J1.130
 +
(NAND on board)
 +
| rowspan="2" |SD1_CMD
 +
| rowspan="2" |CPU.SD1_CMD
 +
| rowspan="2" |L24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_CMD
 +
|-
 +
|ALT5
 +
|GPIO2_IO01
 +
|-
 +
| rowspan="3" |J1.130
 +
(eMMC on board)
 +
| rowspan="3" |NAND_CE1_B
 +
| rowspan="3" |CPU.NAND_CE1_B
 +
| rowspan="3" |G21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CE1_B
 +
|-
 +
|ALT1
 +
|QSPI_A_SS1_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO02
 +
|-
 +
| rowspan="2" |J1.132
 +
(NAND on board)
 +
| rowspan="2" |SD1_RST_B
 +
| rowspan="2" |CPU.SD1_RST_B
 +
| rowspan="2" |R24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_RESET_B
 +
|-
 +
|ALT5
 +
|GPIO2_IO10
 +
|-
 +
| rowspan="3" |J1.132
 +
(eMMC on board)
 +
| rowspan="3" |NAND_CE2_B
 +
| rowspan="3" |CPU.NAND_CE2_B
 +
| rowspan="3" |F21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CE2_B
 +
|-
 +
|ALT1
 +
|QSPI_B_SS0_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO03
 +
|-
 +
| rowspan="2" |J1.134
 +
(NAND on board)
 +
| rowspan="2" |SD1_STROBE
 +
| rowspan="2" |CPU.SD1_STROBE
 +
| rowspan="2" |T24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_STROBE
 +
|-
 +
|ALT5
 +
|GPIO2_IO11
 +
|-
 +
| rowspan="3" |J1.134
 +
(eMMC on board)
 +
| rowspan="3" |NAND_CE3_B
 +
| rowspan="3" |CPU.NAND_CE3_B
 +
| rowspan="3" |H20
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CE3_B
 +
|-
 +
|ALT1
 +
|QSPI_B_SS1_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO034
 +
|-
 +
|J1.136
 +
(NAND on board)
 
|NAND_CLE
 
|NAND_CLE
−
|DGND
+
|CPU.NAND_CLE
 
|H21
 
|H21
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.138
+
| rowspan="3" |J1.136
−
|NAND_DATA00  //  SD1_DATA0
+
(eMMC on board)
−
|CPU.NAND_DATA00 // CPU.SD1_DATA0
+
| rowspan="3" |NAND_CLE
−
|G20  //  M25
+
| rowspan="3" |CPU.NAND_CLE
−
|NVCC_1V8  //  NVCC_3V3 ???
+
| rowspan="3" |H21
−
|I/O
+
| rowspan="3" |NVCC_3V3
−
|???
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CLE
 +
|-
 +
|ALT1
 +
|QSPI_B_SCLK
 
|-
 
|-
−
|J1.140
+
|ALT5
−
|NAND_DATA01  //  SD1_DATA1
+
|GPIO3_IO05
−
|CPU.NAND_DATA01 // CPU.SD1_DATA1
 
−
|J20  //  M24
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.142
+
| rowspan="2" |J1.138
−
|NAND_DATA02  //  SD1_DATA2
+
(NAND on board)
−
|CPU.NAND_DATA02 // CPU.SD1_DATA2
+
| rowspan="2" |SD1_DATA0
−
|H22  //  N25
+
| rowspan="2" |CPU.SD1_DATA0
−
|NVCC_1V8 //  NVCC_3V3 ???
+
| rowspan="2" |M25
−
|I/O
+
| rowspan="2" |NVCC_3V3
−
|???
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA0
 
|-
 
|-
−
|J1.144
+
|ALT5
−
|NAND_DATA03  // SD1_DATA3
+
|GPIO2_IO02
−
|CPU.NAND_DATA03 // CPU.SD1_DATA3
+
|-
−
|J21  //  P25
+
| rowspan="3" |J1.138
−
|NVCC_1V8 //  NVCC_3V3 ???
+
(eMMC on board)
−
|I/O
+
| rowspan="3" |NAND_DATA00
−
|???
+
| rowspan="3" |CPU.NAND_DATA00
−
|
+
| rowspan="3" |G20
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA00
 +
|-
 +
|ALT1
 +
|QSPI_A_DATA0
 +
|-
 +
|ALT5
 +
|GPIO3_IO06
 +
|-
 +
| rowspan="2" |J1.140
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA1
 +
| rowspan="2" |CPU.SD1_DATA1
 +
| rowspan="2" |M24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA1
 +
|-
 +
|ALT5
 +
|GPIO2_IO0
 +
|-
 +
| rowspan="3" |J1.140
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA01
 +
| rowspan="3" |CPU.NAND_DATA01
 +
| rowspan="3" |J20
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA01
 +
|-
 +
|ALT1
 +
|QSPI_A_DATA1
 +
|-
 +
|ALT5
 +
|GPIO3_IO07
 +
|-
 +
| rowspan="2" |J1.142
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA2
 +
| rowspan="2" |CPU.SD1_DATA2
 +
| rowspan="2" |N25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA2
 +
|-
 +
|ALT5
 +
|GPIO2_IO04
 +
|-
 +
| rowspan="3" |J1.142
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA02
 +
| rowspan="3" |CPU.NAND_DATA02
 +
| rowspan="3" |H22
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA02
 +
|-
 +
|ALT1
 +
|QSPI_A_DATA2
 +
|-
 +
|ALT5
 +
|GPIO3_IO08
 +
|-
 +
| rowspan="2" |J1.144
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA3
 +
| rowspan="2" |CPU.SD1_DATA3
 +
| rowspan="2" |P25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA3
 +
|-
 +
|ALT5
 +
|GPIO2_IO05
 +
|-
 +
| rowspan="3" |J1.144
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA03
 +
| rowspan="3" |CPU.NAND_DATA03
 +
| rowspan="3" |J21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA03
 +
|-
 +
|ALT1
 +
|QSPI_A_DATA3
 +
|-
 +
|ALT5
 +
|GPIO3_IO09
 
|-
 
|-
 
|J1.146
 
|J1.146
Line 1,672: Line 2,553:
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
| rowspan="2" |J1.148
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA4
 +
| rowspan="2" |CPU.SD1_DATA4
 +
| rowspan="2" |N24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA4
 
|-
 
|-
−
|J1.148
+
|ALT5
−
|NAND_DATA04  //  SD1_DATA4
+
|GPIO2_IO06
−
|CPU.NAND_DATA04 // CPU.SD1_DATA4
 
−
|L20  //  N24
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.150
+
| rowspan="3" |J1.148
−
|NAND_DATA05  //  SD1_DATA5
+
(eMMC on board)
−
|CPU.NAND_DATA05 // CPU.SD1_DATA5
+
| rowspan="3" |NAND_DATA04
−
|J22  //  P24
+
| rowspan="3" |CPU.NAND_DATA04
−
|NVCC_1V8  //  NVCC_3V3 ???
+
| rowspan="3" |L20
−
|I/O
+
| rowspan="3" |NVCC_3V3
−
|???
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA04
 
|-
 
|-
−
|J1.152
+
|ALT1
−
|NAND_DATA06  //  SD1_DATA6
+
|QSPI_B_DATA0
−
|CPU.NAND_DATA06 // CPU.SD1_DATA6
 
−
|L19  //  R25
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.154
+
|ALT5
−
|NAND_DATA07  //  SD1_DATA7
+
|GPIO3_IO10
−
|CPU.NAND_DATA07 // CPU.SD1_DATA7
 
−
|M19  //  T25
 
−
|NVCC_1V8  //  NVCC_3V3 ???
 
−
|I/O
 
−
|???
 
−
|
 
 
|-
 
|-
−
|J1.156
+
| rowspan="2" |J1.150
−
|NAND_RE_B
+
(NAND on board)
 +
| rowspan="2" |SD1_DATA5
 +
| rowspan="2" |CPU.SD1_DATA5
 +
| rowspan="2" |P24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA5
 +
|-
 +
|ALT5
 +
|GPIO2_IO07
 +
|-
 +
| rowspan="3" |J1.150
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA05
 +
| rowspan="3" |CPU.NAND_DATA05
 +
| rowspan="3" |J22
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA05
 +
|-
 +
|ALT1
 +
|QSPI_B_DATA1
 +
|-
 +
|ALT5
 +
|GPIO3_IO11
 +
|-
 +
| rowspan="2" |J1.152
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA6
 +
| rowspan="2" |CPU.SD1_DATA6
 +
| rowspan="2" |R25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA6
 +
|-
 +
|ALT5
 +
|GPIO2_IO08
 +
|-
 +
| rowspan="3" |J1.152
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA06
 +
| rowspan="3" |CPU.NAND_DATA06
 +
| rowspan="3" |L19
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA06
 +
|-
 +
|ALT1
 +
|QSPI_B_DATA2
 +
|-
 +
|ALT5
 +
|GPIO3_IO12
 +
|-
 +
| rowspan="2" |J1.154
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA7
 +
| rowspan="2" |CPU.SD1_DATA7
 +
| rowspan="2" |T25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA7
 +
|-
 +
|ALT5
 +
|GPIO2_IO09
 +
|-
 +
| rowspan="3" |J1.154
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA07
 +
| rowspan="3" |CPU.NAND_DATA07
 +
| rowspan="3" |M19
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA07
 +
|-
 +
|ALT1
 +
|QSPI_B_DATA3
 +
|-
 +
|ALT5
 +
|GPIO3_IO13
 +
|-
 +
|J1.156
 +
(NAND on board)
 +
|NAND_RE_B
 
|CPU.NAND_RE_B
 
|CPU.NAND_RE_B
 
|K19
 
|K19
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 +
|-
 +
| rowspan="3" |J1.156
 +
(eMMC on board)
 +
| rowspan="3" |NAND_RE_B
 +
| rowspan="3" |CPU.NAND_RE_B
 +
| rowspan="3" |K19
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_RE_B
 +
|-
 +
|ALT1
 +
|QSPI_B_DQS
 +
|-
 +
|ALT5
 +
|GPIO3_IO15
 
|-
 
|-
 
|J1.158
 
|J1.158
 +
(NAND on board)
 
|NAND_READY_B
 
|NAND_READY_B
 
|CPU.NAND_READY_B
 
|CPU.NAND_READY_B
Line 1,724: Line 2,718:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 +
|-
 +
| rowspan="2" |J1.158
 +
(eMMC on board)
 +
| rowspan="2" |NAND_READY_B
 +
| rowspan="2" |CPU.NAND_READY_B
 +
| rowspan="2" |K20
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|RAWNAND_READY_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO16
 
|-
 
|-
 
|J1.160
 
|J1.160
 +
(NAND on board)
 
|NAND_WE_B
 
|NAND_WE_B
 
|CPU.NAND_WE_B
 
|CPU.NAND_WE_B
Line 1,733: Line 2,743:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 +
|-
 +
| rowspan="2" |J1.160
 +
(eMMC on board)
 +
| rowspan="2" |NAND_WE_B
 +
| rowspan="2" |CPU.NAND_WE_B
 +
| rowspan="2" |K22
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|RAWNAND_WE_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO17
 
|-
 
|-
 
|J1.162
 
|J1.162
 +
(NAND on board)
 
|NAND_WP_B
 
|NAND_WP_B
 
|CPU.NAND_WP_B
 
|CPU.NAND_WP_B
Line 1,742: Line 2,768:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 +
|-
 +
| rowspan="2" |J1.162
 +
(eMMC on board)
 +
| rowspan="2" |NAND_WP_B
 +
| rowspan="2" |CPU.NAND_WP_B
 +
| rowspan="2" |K21
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|RAWNAND_WP_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO18
 
|-
 
|-
 
|J1.164
 
|J1.164
Line 1,751: Line 2,792:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,760: Line 2,802:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,769: Line 2,812:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,778: Line 2,822:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,787: Line 2,832:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,796: Line 2,842:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,805: Line 2,852:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,814: Line 2,862:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,823: Line 2,872:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,832: Line 2,882:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,841: Line 2,892:
 
|
 
|
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,850: Line 2,902:
 
| -
 
| -
 
|S
 
|S
 +
|Absolute maximum ratings 5.25V
 
|
 
|
 
|
 
|
Line 1,859: Line 2,912:
 
| -
 
| -
 
|S
 
|S
 +
|Absolute maximum ratings 5.25V
 
|
 
|
 
|
 
|
Line 1,868: Line 2,922:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,877: Line 2,932:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|I
 
|I
 +
|
 
|
 
|
 
|
 
|
Line 1,886: Line 2,942:
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|I
 
|I
 +
|
 
|
 
|
 
|
 
|
Line 1,895: Line 2,952:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,904: Line 2,962:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,913: Line 2,972:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,922: Line 2,982:
 
| -
 
| -
 
|D
 
|D
 +
|
 
|
 
|
 
|
 
|
Line 1,931: Line 2,992:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
Line 1,936: Line 2,998:
 
|}
 
|}
  
−
===Pinout Table J4 pins declaration ===
+
==ONE PIECE J4 pins declaration ==
 
{| class="wikitable"  
 
{| class="wikitable"  
 
! latexfontsize="scriptsize" | Pin  
 
! latexfontsize="scriptsize" | Pin  
Line 1,942: Line 3,004:
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
+
! latexfontsize="scriptsize" | Voltage domain
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
−
! latexfontsize="scriptsize" | Alternative Functions
+
! colspan="2" |Alternative Functions
 
|-
 
|-
 
|J4.1
 
|J4.1
Line 1,953: Line 3,015:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J4.2
+
| rowspan="7" |J4.2
−
|SAI1_RXD7
+
| rowspan="7" |SAI1_RXD7
−
|CPU.SAI1_RXD7
+
| rowspan="7" |CPU.SAI1_RXD7
−
|G1
+
| rowspan="7" |G1
−
|NVCC_3V3
+
| rowspan="7" |NVCC_3V3
−
|I/O
+
| rowspan="7" |I/O
−
|internally used for BOOT config
+
| rowspan="7" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA7
 
|-
 
|-
−
|J4.3
+
|ALT1
−
|SAI1_RXD6
+
|SAI6_MCLK
−
|CPU.SAI1_RXD6
 
−
|G2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.4
+
|ALT2
−
|SAI1_RXD5
+
|SAI1_TX_SYNC
−
|CPU.SAI1_RXD5
 
−
|F1
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.5
+
|ALT3
−
|SAI1_RXD4
+
|SAI1_TX_DATA4
−
|CPU.SAI1_RXD4
 
−
|J1
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.6
+
|ALT4
−
|SAI1_RXD3
+
|CORESIGHT_TRACE7
−
|CPU.SAI1_RXD3
+
|-
−
|J2
+
|ALT5
−
|NVCC_3V3
+
|GPIO4_IO09
−
|I/O
+
|-
−
|internally used for BOOT config
+
|ALT6
−
|
+
|SRC_BOOT_CFG7
 
|-
 
|-
−
|J4.7
+
| rowspan="6" |J4.3
−
|SAI1_RXD2
+
| rowspan="6" |SAI1_RXD6
−
|CPU.SAI1_RXD2
+
| rowspan="6" |CPU.SAI1_RXD6
−
|H2
+
| rowspan="6" |G2
−
|NVCC_3V3
+
| rowspan="6" |NVCC_3V3
−
|I/O
+
| rowspan="6" |I/O
−
|internally used for BOOT config
+
| rowspan="6" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA6
 
|-
 
|-
−
|J4.8
+
|ALT1
−
|SAI1_RXD1
+
|SAI6_TX_SYNC
−
|CPU.SAI1_RXD1
 
−
|L2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.9
+
|ALT2
−
|SAI1_RXD0
+
|SAI6_RX_SYNC
−
|CPU.SAI1_RXD0
 
−
|K2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.10
+
|ALT4
−
|SAI1_RXC
+
|CORESIGHT_TRACE6
−
|CPU.SAI1_RXC
 
−
|K1
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.11
+
|ALT5
−
|SAI1_RXFS
+
|GPIO4_IO08
−
|CPU.SAI1_RXFS
 
−
|L1
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.12
+
|ALT6
−
|DGND
+
|SRC_BOOT_CFG6
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.13
+
| rowspan="7" |J4.4
−
|SAI1_MCLK
+
| rowspan="7" |SAI1_RXD5
−
|CPU.SAI1_MCLK
+
| rowspan="7" |CPU.SAI1_RXD5
−
|
+
| rowspan="7" |F1
−
|NVCC_3V3
+
| rowspan="7" |NVCC_3V3
−
|I/O
+
| rowspan="7" |I/O
−
|
+
| rowspan="7" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA5
 +
|-
 +
|ALT1
 +
|SAI6_TX_DATA0
 
|-
 
|-
−
|J4.14
+
|ALT2
−
|DGND
+
|SAI6_RX_DATA0
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.15
+
|ALT3
−
|SAI1_TXFS
+
|SAI1_RX_SYNC
−
|CPU.SAI1_TXFS
 
−
|H4
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.16
+
|ALT4
−
|SAI1_TXC
+
|CORESIGHT_TRACE5
−
|CPU.SAI1_TXC
 
−
|J5
 
−
|NVCC_3V3
 
−
|I/O
 
−
|
 
−
|
 
 
|-
 
|-
−
|J4.17
+
|ALT5
−
|SAI1_TXD0
+
|GPIO4_IO07
−
|CPU.SAI1_TXD0
 
−
|F2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.18
+
|ALT6
−
|SAI1_TXD1
+
|SRC_BOOT_CFG5
−
|CPU.SAI1_TXD1
 
−
|E2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.19
+
| rowspan="6" |J4.5
−
|SAI1_TXD2
+
| rowspan="6" |SAI1_RXD4
−
|CPU.SAI1_TXD2
+
| rowspan="6" |CPU.SAI1_RXD4
−
|B2
+
| rowspan="6" |J1
−
|NVCC_3V3
+
| rowspan="6" |NVCC_3V3
−
|I/O
+
| rowspan="6" |I/O
−
|internally used for BOOT config
+
| rowspan="6" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA4
 +
|-
 +
|ALT1
 +
|SAI6_TX_BCLK
 +
|-
 +
|ALT2
 +
|SAI6_RX_BCLK
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE4
 +
|-
 +
|ALT5
 +
|GPIO4_IO06
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG4
 +
|-
 +
| rowspan="5" |J4.6
 +
| rowspan="5" |SAI1_RXD3
 +
| rowspan="5" |CPU.SAI1_RXD3
 +
| rowspan="5" |J2
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA3
 
|-
 
|-
−
|J4.20
+
|ALT1
−
|SAI1_TXD3
+
|SAI5_RX_DATA3
−
|CPU.SAI1_TXD3
 
−
|D1
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.21
+
|ALT4
−
|SAI1_TXD4
+
|CORESIGHT_TRACE3
−
|CPU.SAI1_TXD4
 
−
|D2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.22
+
|ALT5
−
|SAI1_TXD5
+
|GPIO4_IO05
−
|CPU.SAI1_TXD5
 
−
|C2
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.23
+
|ALT6
−
|SAI1_TXD6
+
|SRC_BOOT_CFG3
−
|CPU.SAI1_TXD6
 
−
|B3
 
−
|NVCC_3V3
 
−
|I/O
 
−
|internally used for BOOT config
 
−
|
 
 
|-
 
|-
−
|J4.24
+
| rowspan="5" |J4.7
−
|SAI1_TXD7
+
| rowspan="5" |SAI1_RXD2
−
|CPU.SAI1_TXD7
+
| rowspan="5" |CPU.SAI1_RXD2
−
|C1
+
| rowspan="5" |H2
−
|NVCC_3V3
+
| rowspan="5" |NVCC_3V3
−
|I/O
+
| rowspan="5" |I/O
−
|internally used for BOOT config
+
| rowspan="5" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA2
 
|-
 
|-
−
|J4.25
+
|ALT1
−
|DGND
+
|SAI5_RX_DATA2
−
|DGND
+
|-
−
| -
+
|ALT4
−
|<nowiki>-</nowiki>
+
|CORESIGHT_TRACE2
−
|G
+
|-
−
|
+
|ALT5
−
|
+
|GPIO4_IO04
−
|}
 
−
===Pinout Table J5 pins declaration ===
 
−
{| class="wikitable"
 
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! latexfontsize="scriptsize" | Alternative Functions
 
 
|-
 
|-
−
|J5.1
+
|ALT6
−
|DGND
+
|SRC_BOOT_CFG2
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.2
+
| rowspan="5" |J4.8
−
|
+
| rowspan="5" |SAI1_RXD1
−
|
+
| rowspan="5" |CPU.SAI1_RXD1
−
|
+
| rowspan="5" |L2
−
|
+
| rowspan="5" |NVCC_3V3
−
|
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA1
 
|-
 
|-
−
|J5.3
+
|ALT1
−
|
+
|SAI5_RX_DATA1
−
|
+
|-
−
|
+
|ALT4
−
|
+
|CORESIGHT_TRACE1
−
|
+
|-
−
|
+
|ALT5
−
|
+
|GPIO4_IO03
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG1
 +
|-
 +
| rowspan="5" |J4.9
 +
| rowspan="5" |SAI1_RXD0
 +
| rowspan="5" |CPU.SAI1_RXD0
 +
| rowspan="5" |K2
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_RX_DATA0
 +
|-
 +
|ALT1
 +
|SAI5_RX_DATA0
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE0
 +
|-
 +
|ALT5
 +
|GPIO4_IO02
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG0
 +
|-
 +
| rowspan="4" |J4.10
 +
| rowspan="4" |SAI1_RXC
 +
| rowspan="4" |CPU.SAI1_RXC
 +
| rowspan="4" |K1
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI1_RX_BCLK
 +
|-
 +
|ALT1
 +
|SAI5_RX_BCLK
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE_CTL
 +
|-
 +
|ALT5
 +
|GPIO4_IO01
 +
|-
 +
| rowspan="4" |J4.11
 +
| rowspan="4" |SAI1_RXFS
 +
| rowspan="4" |CPU.SAI1_RXFS
 +
| rowspan="4" |L1
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI1_RX_SYNC
 +
|-
 +
|ALT1
 +
|SAI5_RX_SYNC
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE_CLK
 +
|-
 +
|ALT5
 +
|GPIO4_IO00
 
|-
 
|-
−
|J5.4
+
|J4.12
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,218: Line 3,267:
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
| rowspan="4" |J4.13
 +
| rowspan="4" |SAI1_MCLK
 +
| rowspan="4" |CPU.SAI1_MCLK
 +
| rowspan="4" |
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI1_MCLK
 
|-
 
|-
−
|J5.5
+
|ALT1
−
|
+
|SAI5_MCLK
−
|
+
|-
−
|
+
|ALT2
−
|
+
|SAI1_TX_BCLK
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.6
+
|ALT5
−
|
+
|GPIO4_IO20
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.7
+
|J4.14
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,245: Line 3,296:
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
| rowspan="4" |J4.15
 +
| rowspan="4" |SAI1_TXFS
 +
| rowspan="4" |CPU.SAI1_TXFS
 +
| rowspan="4" |H4
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI1_TX_SYNC
 +
|-
 +
|ALT1
 +
|SAI5_TX_SYNC
 
|-
 
|-
−
|J5.8
+
|ALT4
−
|
+
|CORESIGHT_EVENTO
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.9
+
|ALT5
−
|
+
|GPIO4_IO10
−
|
+
|-
−
|
+
| rowspan="4" |J4.16
−
|
+
| rowspan="4" |SAI1_TXC
−
|
+
| rowspan="4" |CPU.SAI1_TXC
−
|
+
| rowspan="4" |J5
−
|
+
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI1_TX_BCLK
 
|-
 
|-
−
|J5.10
+
|ALT1
−
|DGND
+
|SAI5_TX_BCLK
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.11
+
|ALT4
−
|
+
|CORESIGHT_EVENTI
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.12
+
|ALT5
−
|
+
|GPIO4_IO11
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.13
+
| rowspan="5" |J4.17
−
|DGND
+
| rowspan="5" |SAI1_TXD0
−
|DGND
+
| rowspan="5" |CPU.SAI1_TXD0
−
| -
+
| rowspan="5" |F2
−
|<nowiki>-</nowiki>
+
| rowspan="5" |NVCC_3V3
−
|G
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA0
 +
|-
 +
|ALT1
 +
|SAI5_TX_DATA0
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE8
 +
|-
 +
|ALT5
 +
|GPIO4_IO12
 
|-
 
|-
−
|J5.14
+
|ALT6
−
|
+
|SRC_BOOT_CFG8
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.15
+
| rowspan="5" |J4.18
−
|
+
| rowspan="5" |SAI1_TXD1
−
|
+
| rowspan="5" |CPU.SAI1_TXD1
−
|
+
| rowspan="5" |E2
−
|
+
| rowspan="5" |NVCC_3V3
−
|
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA1
 
|-
 
|-
−
|J5.16
+
|ALT1
−
|
+
|SAI5_TX_DATA1
−
|
+
|-
−
|
+
|ALT4
−
|
+
|CORESIGHT_TRACE9
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.17
+
|ALT5
−
|
+
|GPIO4_IO13
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.18
+
|ALT6
−
|DGND
+
|SRC_BOOT_CFG9
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.19
+
| rowspan="5" |J4.19
−
|
+
| rowspan="5" |SAI1_TXD2
−
|
+
| rowspan="5" |CPU.SAI1_TXD2
−
|
+
| rowspan="5" |B2
−
|
+
| rowspan="5" |NVCC_3V3
−
|
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |Internally used for BOOT config
−
|
+
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA2
 
|-
 
|-
−
|J5.20
+
|ALT1
−
|
+
|SAI5_TX_DATA2
−
|
+
|-
−
|
+
|ALT4
−
|
+
|CORESIGHT_TRACE10
−
|
+
|-
−
|
+
|ALT5
−
|
+
|GPIO4_IO14
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG10
 +
|-
 +
| rowspan="5" |J4.20
 +
| rowspan="5" |SAI1_TXD3
 +
| rowspan="5" |CPU.SAI1_TXD3
 +
| rowspan="5" |D1
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA3
 +
|-
 +
|ALT1
 +
|SAI5_TX_DATA3
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE11
 +
|-
 +
|ALT5
 +
|GPIO4_IO15
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG11
 +
|-
 +
| rowspan="6" |J4.21
 +
| rowspan="6" |SAI1_TXD4
 +
| rowspan="6" |CPU.SAI1_TXD4
 +
| rowspan="6" |D2
 +
| rowspan="6" |NVCC_3V3
 +
| rowspan="6" |I/O
 +
| rowspan="6" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA4
 +
|-
 +
|ALT1
 +
|SAI6_RX_BCLK
 +
|-
 +
|ALT2
 +
|SAI6_TX_BCLK
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE12
 +
|-
 +
|ALT5
 +
|GPIO4_IO16
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG12
 +
|-
 +
| rowspan="6" |J4.22
 +
| rowspan="6" |SAI1_TXD5
 +
| rowspan="6" |CPU.SAI1_TXD5
 +
| rowspan="6" |C2
 +
| rowspan="6" |NVCC_3V3
 +
| rowspan="6" |I/O
 +
| rowspan="6" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA5
 +
|-
 +
|ALT1
 +
|SAI6_RX_DATA0
 +
|-
 +
|ALT2
 +
|SAI6_TX_DATA0
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE13
 
|-
 
|-
−
|J5.21
+
|ALT5
−
|
+
|GPIO4_IO17
−
|
+
|-
−
|
+
|ALT6
 +
|SRC_BOOT_CFG13
 +
|-
 +
| rowspan="6" |J4.23
 +
| rowspan="6" |SAI1_TXD6
 +
| rowspan="6" |CPU.SAI1_TXD6
 +
| rowspan="6" |B3
 +
| rowspan="6" |NVCC_3V3
 +
| rowspan="6" |I/O
 +
| rowspan="6" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA6
 +
|-
 +
|ALT1
 +
|SAI6_RX_SYNC
 +
|-
 +
|ALT2
 +
|SAI6_TX_SYNC
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE14
 +
|-
 +
|ALT5
 +
|GPIO4_IO18
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG14
 +
|-
 +
| rowspan="5" |J4.24
 +
| rowspan="5" |SAI1_TXD7
 +
| rowspan="5" |CPU.SAI1_TXD7
 +
| rowspan="5" |C1
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 +
| rowspan="5" |Internally used for BOOT config
 +
Could be pulled-up or down during bootstrap.
 +
|ALT0
 +
|SAI1_TX_DATA7
 +
|-
 +
|ALT1
 +
|SAI6_MCLK
 +
|-
 +
|ALT4
 +
|CORESIGHT_TRACE15
 +
|-
 +
|ALT5
 +
|GPIO4_IO19
 +
|-
 +
|ALT6
 +
|SRC_BOOT_CFG15
 +
|-
 +
|J4.25
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
 +
|
 +
|
 +
|}
 +
 +
==ONE PIECE J5 pins declaration ==
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" | Voltage domain
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! colspan="2" |Alternative Functions
 +
|-
 +
|J5.1
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
|J5.2
 +
|PCIE2_RXN
 +
|CPU.PCIE2_RXN_N
 +
|D24
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.3
 +
|PCIE2_RXP
 +
|CPU.PCIE2_RXN_P
 +
|D25
 +
| -
 +
|D
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J5.22
+
|J5.4
−
|
+
|DGND
−
|
+
|DGND
−
|
+
| -
−
|
+
|<nowiki>-</nowiki>
−
|
+
|G
−
|
+
|
−
|
+
|
 +
|
 +
|-
 +
|J5.5
 +
|PCIE2_TXN
 +
|CPU.PCIE2_TXN_N
 +
|E24
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.6
 +
|PCIE2_TXP
 +
|CPU.PCIE2_TXN_P
 +
|E25
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.7
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
|J5.8
 +
|PCIE2_REF_CLKN
 +
|CPU.PCIE2_REF_PAD_CLK_N
 +
|F24
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.9
 +
|PCIE2_REF_CLKP
 +
|CPU.PCIE2_REF_PAD_CLK_P
 +
|F25
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.10
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
|J5.11
 +
|CSI_P2_CKN
 +
|CPU.MIPI_CSI2_CLK_N
 +
|A19
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.12
 +
|CSI_P2_CKP
 +
|CPU.MIPI_CSI2_CLK_P
 +
|B19
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.13
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
|J5.14
 +
|CSI_P2_DN0
 +
|CPU.MIPI_CSI2_D0_N
 +
|C20
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.15
 +
|CSI_P2_DP0
 +
|CPU.MIPI_CSI2_D0_P
 +
|D10
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.16
 +
|CSI_P2_DN1
 +
|CPU.MIPI_CSI2_D1_N
 +
|A20
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.17
 +
|CSI_P2_DP1
 +
|CPU.MIPI_CSI2_D1_P
 +
|B20
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.18
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
|J5.19
 +
|CSI_P2_DN2
 +
|CPU.MIPI_CSI2_D2_N
 +
|A21
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.20
 +
|CSI_P2_DP2
 +
|CPU.MIPI_CSI2_D2_P
 +
|B21
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.21
 +
|CSI_P2_DN3
 +
|CPU.MIPI_CSI2_D3_N
 +
|C19
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.22
 +
|CSI_P2_DP3
 +
|CPU.MIPI_CSI2_D3_P
 +
|D19
 +
| -
 +
|D
 +
|
 +
|
 +
|
 +
|-
 +
|J5.23
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
| rowspan="4" |J5.24
 +
| rowspan="4" |I2C4_SCL
 +
| rowspan="4" |CPU.I2C4_SCL
 +
| rowspan="4" |F8
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|I2C4_SCL
 +
|-
 +
|ALT1
 +
|PWM2_OUT
 +
|-
 +
|ALT2
 +
|PCIE1_CLKREQ_B
 +
|-
 +
|ALT5
 +
|GPIO5_IO20
 +
|-
 +
| rowspan="4" |J5.25
 +
| rowspan="4" |I2C4_SDA
 +
| rowspan="4" |CPU.I2C4_SDA
 +
| rowspan="4" |F9
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|I2C4_SDA
 
|-
 
|-
−
|J5.23
+
|ALT1
−
|DGND
+
|PWM1_OUT
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.24
+
|ALT2
−
|
+
|PCIE2_CLKREQ_B
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J5.25
+
|ALT5
−
|
+
|GPIO5_IO21
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|}
 
|}
  

Latest revision as of 17:49, 28 December 2023

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History
Issue Date Notes

2020/09/29

First release
2021/02/02 Add pull-up/down information


Connectors and Pinout Table description[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on MITO 8M SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM edge connector 204 pin partially compatible with AXEL Lite SOM TE Connectivity 2-2013289-1
J4 ONE PIECE connector single row 25pins SAMTEC FSI-125-03-G-S-AD-TR
J5 ONE PIECE connector single row 25pins SAMTEC FSI-125-03-G-S-AD-TR

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference:

MITO 8M TOP view
MITO 8M BOTTOM view

Below a detailed description of the pinout, grouped in the following tables:

  • two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
  • a dedicated tables for J4 one-piece connector
  • a dedicated tables for J5 one-piece connector

Pinout Table description[edit | edit source]

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the MITO 8M connectors
Internal
connections 		Connections to the components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
  • LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

SODIMM J1 ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6 NVCC_3V3 I/O ALT0 GPIO1_IO00
ALT1 CCM_ENET_PHY_REF_CLK_ROOT
ALT5 ANAMIX_REF_CLK_32K
ALT6 CCM_EXT_CLK1
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7 NVCC_3V3 I/O Internally used for ETH PHY reset, do not connect ALT0 GPIO1_IO01
ALT1 PWM1_OUT
ALT5 ANAMIX_REF_CLK_25M
ALT6 CCM_EXT_CLK2
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6 NVCC_3V3 I/O ALT0 SPDIF1_EXT_CLK
ALT1 PWM1_OUT
ALT5 GPIO5_IO05
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6 NVCC_3V3 I/O Internally used, do not connect ALT0 GPIO1_IO13
ALT1 USB1_OTG_OC
ALT5 PWM2_OUT
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5 NVCC_3V3 I/O ALT0 ECSPI2_SCLK
ALT1 UART4_RX
ALT5 GPIO5_IO10
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5 NVCC_3V3 I/O ALT0 ECSPI2_MOSI
ALT1 UART4_TX
ALT5 GPIO5_IO11
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7 NVCC_3V3 I/O ALT0 GPIO1_IO08
ALT1 ENET1_1588_EVENT0_IN
ALT5 USDHC2_RESET_B
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7 NVCC_3V3 I/O ALT0 GPIO1_IO09
ALT1 ENET1_1588_EVENT0_OUT
ALT5 SDMA2_EXT_EVENT0
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5 NVCC_3V3 I/O ALT0 ECSPI2_MISO
ALT1 UART4_CTS_B
ALT5 GPIO5_IO12
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5 NVCC_3V3 I/O ALT0 ECSPI2_SS0
ALT1 UART4_RTS_B
ALT5 GPIO5_IO13
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7 NVCC_3V3 I/O Internally used for MIPI-to-LVDS interrupt, do not connect

Pulled-up to NVCC_3V3

ALT0 GPIO1_IO05
ALT1 M4_NMI
ALT5 CCM_PMIC_READY
J1.63 I2C2_SCL CPU.I2C2_SCL G7 NVCC_3V3 I/O ALT0 I2C2_SCL
ALT1 ENET1_1588_EVENT1_IN
ALT5 GPIO5_IO16
J1.65 I2C2_SDA CPU.I2C2_SDA F7 NVCC_3V3 I/O ALT0 I2C2_SDA
ALT1 ENET1_1588_EVENT1_OUT
ALT5 GPIO5_IO17
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5 NVCC_3V3 I/O Internally used for MIPI-to-LVDS enable, do not connect ALT0 GPIO1_IO06
ALT1 ENET1_MDC
ALT5 USDHC1_CD_B
ALT6 CCM_EXT_CLK3
J1.69 SAI2_RXC CPU.SAI2_RXC H3 NVCC_3V3 I/O ALT0 SAI2_RX_BCLK
ALT1 SAI5_TX_BCLK
ALT5 GPIO4_IO22
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4 NVCC_3V3 I/O ALT0 SAI2_RX_SYNC
ALT1 SAI5_TX_SYNC
ALT5 GPIO4_IO21
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22 NVCC_3V3 I/O ALT0 USDHC2_DATA0
ALT5 GPIO2_IO15
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21 NVCC_3V3 I/O ALT0 USDHC2_DATA1
ALT5 GPIO2_IO16
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22 NVCC_3V3 I/O ALT0 USDHC2_DATA2
ALT5 GPIO2_IO17
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21 NVCC_3V3 I/O ALT0 USDHC2_DATA3
ALT5 GPIO2_IO18
J1.83 SD2_CMD CPU.SD2_CMD M22 NVCC_3V3 I/O ALT0 USDHC2_CMD
ALT5 GPIO2_IO14
J1.85 SD2_CLK CPU.SD2_CLK L22 NVCC_3V3 I/O ALT0 USDHC2_CLK
ALT5 GPIO2_IO13
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7 NVCC_3V3 I/O ALT0 UART3_TX
ALT1 UART1_RTS_B
ALT5 GPIO5_IO27
J1.91 UART3_RXD CPU.UART3_RXD A6 NVCC_3V3 I/O ALT0 UART3_RX
ALT1 UART1_CTS_B
ALT5 GPIO5_IO26
J1.93 UART4_TXD CPU.UART4_TXD D7 NVCC_3V3 I/O ALT0 UART4_TX
ALT1 UART2_RTS_B
ALT2 PCIE2_CLKREQ_B
ALT5 GPIO5_IO29
J1.95 UART4_RXD CPU.UART4_RXD C6 NVCC_3V3 I/O ALT0 UART4_RX
ALT1 UART2_CTS_B
ALT2 PCIE1_CLKREQ_B
ALT5 GPIO5_IO28
J1.97 SD2_WP CPU.SD2_WP M21 NVCC_3V3 I/O ALT0 USDHC2_WP
ALT5 GPIO2_IO20
J1.99 SD2_RST_B CPU.SD2_RESET_B R22 NVCC_3V3 I/O ALT0 USDHC2_RESET_B
ALT5 GPIO2_IO19
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3 VDD_PHY_1V8 I/O
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3 VDD_PHY_1V8 I/O
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 - D connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 - D connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 - D connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 - D connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 - D connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 - D connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 - D connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 - D connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 - D connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 - D connected with capacitor in series
J1.127 HDMI_CEC CPU.HDMI_CEC W3 VDD_PHY_1V8 I/O
J1.129 HDMI_HPD CPU.HDMI_HPD W2 VDD_PHY_1V8 I/O
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B L21 NVCC_3V3 I/O ALT0 USDHC2_CD_B
ALT5 GPIO2_IO12
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 D4 NVCC_3V3 I/O ALT0 ECSPI1_SS0
ALT1 UART3_RTS_B
ALT5 GPIO5_IO09
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D5 NVCC_3V3 I/O ALT0 ECSPI1_SCLK
ALT1 UART3_RX
ALT5 GPIO5_IO06
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO B4 NVCC_3V3 I/O ALT0 ECSPI1_MISO
ALT1 UART3_CTS_B
ALT5 GPIO5_IO08
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 P4 NVCC_3V3 I/O ALT0 GPIO1_IO03
ALT1 USDHC1_VSELECT
ALT5 SDMA1_EXT_EVENT0
J1.187 UART2_TXD CPU.UART2_TXD D6 NVCC_3V3 I/O used as default Linux console ALT0 UART2_TX
ALT1 ECSPI3_SS0
ALT5 GPIO5_IO25
J1.189 UART2_RXD CPU.UART2_RXD B6 NVCC_3V3 I/O used as default Linux console ALT0 UART2_RXD
ALT1 ECSPI3_MISO
ALT5 GPIO5_IO24
J1.191 UART1_TXD CPU.UART1_TXD A7 NVCC_3V3 I/O ALT0 UART1_TX
ALT1 ECSPI3_MOSI
ALT5 GPIO5_IO23
J1.193 UART1_RXD CPU.UART1_RXD C7 NVCC_3V3 I/O ALT0 UART1_RXD
ALT1 ECSPI3_SCLK
ALT5 GPIO5_IO22
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI A4 NVCC_3V3 I/O ALT0 ECSPI1_MOSI
ALT1 UART3_TX
ALT5 GPIO5_IO07
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 K7 NVCC_3V3 I/O ALT0 GPIO1_IO14
ALT1 USB2_OTG_PWR
ALT5 PWM3_OUT
ALT6 CCM_CLKO1
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 P5 NVCC_3V3 I/O ALT0 GPIO1_IO04
ALT1 USDHC2_VSELECT
ALT5 SDMA1_EXT_EVENT1
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 L7 NVCC_3V3 I/O ALT0 GPIO1_IO12
ALT1 USB1_OTG_PWR
ALT5 SDMA2_EXT_EVENT1
J1.203 DGND DGND - - G

SODIMM J1 EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30 - S
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS I internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
J1.24 EXT_RESET MASTER RESET - - I internal pull-up to NVCC_SNVS
J1.26 SAI3_RXC CPU.SAI3_RXC F4 NVCC_3V3 I/O ALT0 SAI3_RX_BCLK
ALT1 GPT1_CAPTURE2
ALT2 SAI5_RX_BCLK
ALT5 GPIO4_IO29
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 R4 NVCC_3V3 I/O Internally used for SW reset, do not connect ALT0 GPIO1_IO02
ALT1 WDOG1_WDOG_B
ALT5 WDOG1_WDOG_ANY
ALT7 SJC_DE_B
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD F3 NVCC_3V3 I/O ALT0 SAI3_RX_DATA0
ALT1 GPT1_COMPARE1
ALT2 SAI5_RX_DATA0
ALT5 GPIO4_IO30
J1.34 SAI2_MCLK CPU.SAI2_MCLK H5 NVCC_3V3 I/O ALT0 SAI2_MCLK
ALT1 SAI5_MCLK
ALT5 GPIO4_IO27
J1.36 SAI3_RXFS CPU.SAI3_RXFS G4 NVCC_3V3 I/O ALT0 SAI3_RX_SYNC
ALT1 GPT1_CAPTURE1
ALT2 SAI5_RX_SYNC
ALT5 GPIO4_IO28
J1.38 I2C3_SCL CPU.I2C3_SCL G8 NVCC_3V3 I/O ALT0 I2C3_SCL
ALT1 PWM4_OUT
ALT2 GPT2_CLK
ALT5 GPIO5_IO18
J1.40 SAI3_TXFS CPU.SAI3_TXFS G3 NVCC_3V3 I/O ALT0 SAI3_TX_SYNC
ALT1 GPT1_CLK
ALT2 SAI5_RX_DATA1
ALT5 GPIO4_IO31
J1.42 SPDIF_RX CPU.SPDIF_RX G6 NVCC_3V3 I/O ALT0 SPDIF1_IN
ALT1 PWM2_OUT
ALT5 GPIO5_IO04
J1.44 SPDIF_TX CPU.SPDIF_TX F6 NVCC_3V3 I/O ALT0 SPDIF1_OUT
ALT1 PWM3_OUT
ALT5 GPIO5_IO03
J1.46 SAI3_MCLK CPU.SAI3_MCLK D3 NVCC_3V3 I/O ALT0 SAI3_MCLK
ALT1 PWM4_OUT
ALT2 SAI5_MCLK
ALT5 GPIO5_IO02
J1.48 I2C3_SDA CPU.I2C3_SDA E9 NVCC_3V3 I/O ALT0 I2C3_SDA
ALT1 PWM3_OUT
ALT2 GPT3_CLK
ALT5 GPIO5_IO19
J1.50 SAI3_TXC CPU.SAI3_TXC C4 NVCC_3V3 I/O ALT0 SAI3_TX_BCLK
ALT1 GPT1_COMPARE2
ALT2 SAI5_RX_DATA2
ALT5 GPIO5_IO00
J1.52 SAI3_TXD CPU.SAI3_TXD C3 NVCC_3V3 I/O ALT0 SAI3_TX_DATA0
ALT1 GPT1_COMPARE3
ALT2 SAI5_RX_DATA3
ALT5 GPIO5_IO01
J1.54 GPIO1_IO10 CPU.GPIO1_IO10 M7 NVCC_3V3 I/O Internally used for ETH PHY interrupt, do not connect ALT0 GPIO1_IO10
ALT1 USB1_OTG_ID
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK K4 NVCC_3V3 I/O ALT0 SAI5_MCLK
ALT1 SAI1_TX_BCLK
ALT2 SAI4_MCLK
ALT5 GPIO3_IO25
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 J6 NVCC_3V3 I/O ALT0 GPIO1_IO15
ALT1 USB2_OTG_OC
ALT5 PWM4_OUT
ALT6 CCM_CLKO2
J1.62 SAI5_RXFS CPU.SAI5_RXFS N4 NVCC_3V3 I/O ALT0 SAI5_RX_SYNC
ALT1 SAI1_TX_DATA0
ALT5 GPIO3_IO19
J1.64 SAI5_RXC CPU.SAI5_RXC L5 NVCC_3V3 I/O ALT0 SAI5_RX_BCLK
ALT1 SAI1_TX_DATA1
ALT5 GPIO3_IO20
J1.66 SAI2_TXC CPU.SAI2_TXC J5 NVCC_3V3 I/O ALT0 SAI2_TX_BCLK
ALT1 SAI5_TX_DATA2
ALT5 GPIO4_IO25
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 G5 NVCC_3V3 I/O ALT0 SAI2_TX_DATA0
ALT1 SAI5_TX_DATA3
ALT5 GPIO4_IO26
J1.70 SAI2_TXFS CPU.SAI2_TXFS H4 NVCC_3V3 I/O ALT0 SAI2_TX_SYNC
ALT1 SAI5_TX_DATA1
ALT5 GPIO4_IO24
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 H6 NVCC_3V3 I/O ALT0 SAI2_RX_DATA0
ALT1 SAI5_TX_DATA0
ALT5 GPIO4_IO23
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 M5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0
ALT1 SAI1_TX_DATA2
ALT5 GPIO3_IO21
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 L4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1
ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_SYNC
ALT5 GPIO3_IO212
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 M4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA2
ALT1 SAI1_TX_DATA4
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_BCLK
ALT5 GPIO3_IO23
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 K5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA3
ALT1 SAI1_TX_DATA5
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_DATA0
ALT5 GPIO3_IO24
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N T22 VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.86 CLK2_P CPU.CLK2_P U22 VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N K24 VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P K25 VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N H24 VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P H25 VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N J24 VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P J25 VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N A22 - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P B22 - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N A23 - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P B23 - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N C22 - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P D22 - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N B24 - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P C23 - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N C21 - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P D21 - D
J1.122 DGND DGND - - G
J1.124

(NAND on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.124

(eMMC on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O ALT0 RAWNAND_DQS
ALT1 QSPI_A_DQS
ALT5 GPIO3_IO14
J1.126

(NAND on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.126

(eMMC on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O ALT0 RAWNAND_ALE
ALT1 QSPI_A_SCLK
ALT5 GPIO3_IO00
J1.128

(NAND on board)

SD1_CLK CPU.SD1_CLK L25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CLK
ALT5 GPIO2_IO00
J1.128

(eMMC on board)

NAND_CE0_B CPU.NAND_CE0_B H19 NVCC_3V3 I/O ALT0 RAWNAND_CE0_B
ALT1 QSPI_A_SS0_B
ALT5 GPIO3_IO01
J1.130

(NAND on board)

SD1_CMD CPU.SD1_CMD L24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CMD
ALT5 GPIO2_IO01
J1.130

(eMMC on board)

NAND_CE1_B CPU.NAND_CE1_B G21 NVCC_3V3 I/O ALT0 RAWNAND_CE1_B
ALT1 QSPI_A_SS1_B
ALT5 GPIO3_IO02
J1.132

(NAND on board)

SD1_RST_B CPU.SD1_RST_B R24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_RESET_B
ALT5 GPIO2_IO10
J1.132

(eMMC on board)

NAND_CE2_B CPU.NAND_CE2_B F21 NVCC_3V3 I/O ALT0 RAWNAND_CE2_B
ALT1 QSPI_B_SS0_B
ALT5 GPIO3_IO03
J1.134

(NAND on board)

SD1_STROBE CPU.SD1_STROBE T24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_STROBE
ALT5 GPIO2_IO11
J1.134

(eMMC on board)

NAND_CE3_B CPU.NAND_CE3_B H20 NVCC_3V3 I/O ALT0 RAWNAND_CE3_B
ALT1 QSPI_B_SS1_B
ALT5 GPIO3_IO034
J1.136

(NAND on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.136

(eMMC on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O ALT0 RAWNAND_CLE
ALT1 QSPI_B_SCLK
ALT5 GPIO3_IO05
J1.138

(NAND on board)

SD1_DATA0 CPU.SD1_DATA0 M25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA0
ALT5 GPIO2_IO02
J1.138

(eMMC on board)

NAND_DATA00 CPU.NAND_DATA00 G20 NVCC_3V3 I/O ALT0 RAWNAND_DATA00
ALT1 QSPI_A_DATA0
ALT5 GPIO3_IO06
J1.140

(NAND on board)

SD1_DATA1 CPU.SD1_DATA1 M24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA1
ALT5 GPIO2_IO0
J1.140

(eMMC on board)

NAND_DATA01 CPU.NAND_DATA01 J20 NVCC_3V3 I/O ALT0 RAWNAND_DATA01
ALT1 QSPI_A_DATA1
ALT5 GPIO3_IO07
J1.142

(NAND on board)

SD1_DATA2 CPU.SD1_DATA2 N25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA2
ALT5 GPIO2_IO04
J1.142

(eMMC on board)

NAND_DATA02 CPU.NAND_DATA02 H22 NVCC_3V3 I/O ALT0 RAWNAND_DATA02
ALT1 QSPI_A_DATA2
ALT5 GPIO3_IO08
J1.144

(NAND on board)

SD1_DATA3 CPU.SD1_DATA3 P25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA3
ALT5 GPIO2_IO05
J1.144

(eMMC on board)

NAND_DATA03 CPU.NAND_DATA03 J21 NVCC_3V3 I/O ALT0 RAWNAND_DATA03
ALT1 QSPI_A_DATA3
ALT5 GPIO3_IO09
J1.146 DGND DGND - - G
J1.148

(NAND on board)

SD1_DATA4 CPU.SD1_DATA4 N24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA4
ALT5 GPIO2_IO06
J1.148

(eMMC on board)

NAND_DATA04 CPU.NAND_DATA04 L20 NVCC_3V3 I/O ALT0 RAWNAND_DATA04
ALT1 QSPI_B_DATA0
ALT5 GPIO3_IO10
J1.150

(NAND on board)

SD1_DATA5 CPU.SD1_DATA5 P24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA5
ALT5 GPIO2_IO07
J1.150

(eMMC on board)

NAND_DATA05 CPU.NAND_DATA05 J22 NVCC_3V3 I/O ALT0 RAWNAND_DATA05
ALT1 QSPI_B_DATA1
ALT5 GPIO3_IO11
J1.152

(NAND on board)

SD1_DATA6 CPU.SD1_DATA6 R25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA6
ALT5 GPIO2_IO08
J1.152

(eMMC on board)

NAND_DATA06 CPU.NAND_DATA06 L19 NVCC_3V3 I/O ALT0 RAWNAND_DATA06
ALT1 QSPI_B_DATA2
ALT5 GPIO3_IO12
J1.154

(NAND on board)

SD1_DATA7 CPU.SD1_DATA7 T25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA7
ALT5 GPIO2_IO09
J1.154

(eMMC on board)

NAND_DATA07 CPU.NAND_DATA07 M19 NVCC_3V3 I/O ALT0 RAWNAND_DATA07
ALT1 QSPI_B_DATA3
ALT5 GPIO3_IO13
J1.156

(NAND on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.156

(eMMC on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O ALT0 RAWNAND_RE_B
ALT1 QSPI_B_DQS
ALT5 GPIO3_IO15
J1.158

(NAND on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.158

(eMMC on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O ALT0 RAWNAND_READY_B
ALT5 GPIO3_IO16
J1.160

(NAND on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.160

(eMMC on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O ALT0 RAWNAND_WE_B
ALT5 GPIO3_IO17
J1.162

(NAND on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.162

(eMMC on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O ALT0 RAWNAND_WP_B
ALT5 GPIO3_IO18
J1.164 DGND DGND - - G
J1.166 CLK1_N CPU.CLK1_N T23 D
J1.168 CLK1_P CPU.CLK1_P R23 D
J1.170 USB2_RXN CPU.USB2_RX_N B8 D
J1.172 USB2_RXP CPU.USB2_RX_P A8 D
J1.174 USB2_TXN CPU.USB2_TX_N B9 D
J1.176 USB2_TXP CPU.USB2_TX_P A9 D
J1.178 USB1_RXN CPU.USB1_RX_N B12 D
J1.180 USB1_RXP CPU.USB1_RX_P A12 D
J1.182 USB1_TXN CPU.USB1_TX_N B13 D
J1.184 USB1_TXP CPU.USB1_TX_P A13 D
J1.186 USB1_VBUS CPU.USB1_VBUS D14 - S Absolute maximum ratings 5.25V
J1.188 USB2_VBUS CPU.USB2_VBUS D9 - S Absolute maximum ratings 5.25V
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C14 VDD_PHY_3V3 I
J1.194 USB2_ID CPU.USB2_ID C9 VDD_PHY_3V3 I
J1.196 USB1_DN CPU.USB1_DN B14 - D
J1.198 USB1_DP CPU.USB1_DP A14 - D
J1.200 USB2_DP CPU.USB2_DP A10 - D
J1.202 USB2_DN CPU.USB2_DN B10 - D
J1.204 DGND DGND - - G

ONE PIECE J4 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J4.1 DGND DGND - - G
J4.2 SAI1_RXD7 CPU.SAI1_RXD7 G1 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA7
ALT1 SAI6_MCLK
ALT2 SAI1_TX_SYNC
ALT3 SAI1_TX_DATA4
ALT4 CORESIGHT_TRACE7
ALT5 GPIO4_IO09
ALT6 SRC_BOOT_CFG7
J4.3 SAI1_RXD6 CPU.SAI1_RXD6 G2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA6
ALT1 SAI6_TX_SYNC
ALT2 SAI6_RX_SYNC
ALT4 CORESIGHT_TRACE6
ALT5 GPIO4_IO08
ALT6 SRC_BOOT_CFG6
J4.4 SAI1_RXD5 CPU.SAI1_RXD5 F1 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA5
ALT1 SAI6_TX_DATA0
ALT2 SAI6_RX_DATA0
ALT3 SAI1_RX_SYNC
ALT4 CORESIGHT_TRACE5
ALT5 GPIO4_IO07
ALT6 SRC_BOOT_CFG5
J4.5 SAI1_RXD4 CPU.SAI1_RXD4 J1 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA4
ALT1 SAI6_TX_BCLK
ALT2 SAI6_RX_BCLK
ALT4 CORESIGHT_TRACE4
ALT5 GPIO4_IO06
ALT6 SRC_BOOT_CFG4
J4.6 SAI1_RXD3 CPU.SAI1_RXD3 J2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA3
ALT1 SAI5_RX_DATA3
ALT4 CORESIGHT_TRACE3
ALT5 GPIO4_IO05
ALT6 SRC_BOOT_CFG3
J4.7 SAI1_RXD2 CPU.SAI1_RXD2 H2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA2
ALT1 SAI5_RX_DATA2
ALT4 CORESIGHT_TRACE2
ALT5 GPIO4_IO04
ALT6 SRC_BOOT_CFG2
J4.8 SAI1_RXD1 CPU.SAI1_RXD1 L2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA1
ALT1 SAI5_RX_DATA1
ALT4 CORESIGHT_TRACE1
ALT5 GPIO4_IO03
ALT6 SRC_BOOT_CFG1
J4.9 SAI1_RXD0 CPU.SAI1_RXD0 K2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_RX_DATA0
ALT1 SAI5_RX_DATA0
ALT4 CORESIGHT_TRACE0
ALT5 GPIO4_IO02
ALT6 SRC_BOOT_CFG0
J4.10 SAI1_RXC CPU.SAI1_RXC K1 NVCC_3V3 I/O ALT0 SAI1_RX_BCLK
ALT1 SAI5_RX_BCLK
ALT4 CORESIGHT_TRACE_CTL
ALT5 GPIO4_IO01
J4.11 SAI1_RXFS CPU.SAI1_RXFS L1 NVCC_3V3 I/O ALT0 SAI1_RX_SYNC
ALT1 SAI5_RX_SYNC
ALT4 CORESIGHT_TRACE_CLK
ALT5 GPIO4_IO00
J4.12 DGND DGND - - G
J4.13 SAI1_MCLK CPU.SAI1_MCLK NVCC_3V3 I/O ALT0 SAI1_MCLK
ALT1 SAI5_MCLK
ALT2 SAI1_TX_BCLK
ALT5 GPIO4_IO20
J4.14 DGND DGND - - G
J4.15 SAI1_TXFS CPU.SAI1_TXFS H4 NVCC_3V3 I/O ALT0 SAI1_TX_SYNC
ALT1 SAI5_TX_SYNC
ALT4 CORESIGHT_EVENTO
ALT5 GPIO4_IO10
J4.16 SAI1_TXC CPU.SAI1_TXC J5 NVCC_3V3 I/O ALT0 SAI1_TX_BCLK
ALT1 SAI5_TX_BCLK
ALT4 CORESIGHT_EVENTI
ALT5 GPIO4_IO11
J4.17 SAI1_TXD0 CPU.SAI1_TXD0 F2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA0
ALT1 SAI5_TX_DATA0
ALT4 CORESIGHT_TRACE8
ALT5 GPIO4_IO12
ALT6 SRC_BOOT_CFG8
J4.18 SAI1_TXD1 CPU.SAI1_TXD1 E2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA1
ALT1 SAI5_TX_DATA1
ALT4 CORESIGHT_TRACE9
ALT5 GPIO4_IO13
ALT6 SRC_BOOT_CFG9
J4.19 SAI1_TXD2 CPU.SAI1_TXD2 B2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA2
ALT1 SAI5_TX_DATA2
ALT4 CORESIGHT_TRACE10
ALT5 GPIO4_IO14
ALT6 SRC_BOOT_CFG10
J4.20 SAI1_TXD3 CPU.SAI1_TXD3 D1 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA3
ALT1 SAI5_TX_DATA3
ALT4 CORESIGHT_TRACE11
ALT5 GPIO4_IO15
ALT6 SRC_BOOT_CFG11
J4.21 SAI1_TXD4 CPU.SAI1_TXD4 D2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA4
ALT1 SAI6_RX_BCLK
ALT2 SAI6_TX_BCLK
ALT4 CORESIGHT_TRACE12
ALT5 GPIO4_IO16
ALT6 SRC_BOOT_CFG12
J4.22 SAI1_TXD5 CPU.SAI1_TXD5 C2 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA5
ALT1 SAI6_RX_DATA0
ALT2 SAI6_TX_DATA0
ALT4 CORESIGHT_TRACE13
ALT5 GPIO4_IO17
ALT6 SRC_BOOT_CFG13
J4.23 SAI1_TXD6 CPU.SAI1_TXD6 B3 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA6
ALT1 SAI6_RX_SYNC
ALT2 SAI6_TX_SYNC
ALT4 CORESIGHT_TRACE14
ALT5 GPIO4_IO18
ALT6 SRC_BOOT_CFG14
J4.24 SAI1_TXD7 CPU.SAI1_TXD7 C1 NVCC_3V3 I/O Internally used for BOOT config

Could be pulled-up or down during bootstrap.

ALT0 SAI1_TX_DATA7
ALT1 SAI6_MCLK
ALT4 CORESIGHT_TRACE15
ALT5 GPIO4_IO19
ALT6 SRC_BOOT_CFG15
J4.25 DGND DGND - - G

ONE PIECE J5 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J5.1 DGND DGND - - G
J5.2 PCIE2_RXN CPU.PCIE2_RXN_N D24 - D
J5.3 PCIE2_RXP CPU.PCIE2_RXN_P D25 - D
J5.4 DGND DGND - - G
J5.5 PCIE2_TXN CPU.PCIE2_TXN_N E24 - D
J5.6 PCIE2_TXP CPU.PCIE2_TXN_P E25 - D
J5.7 DGND DGND - - G
J5.8 PCIE2_REF_CLKN CPU.PCIE2_REF_PAD_CLK_N F24 - D
J5.9 PCIE2_REF_CLKP CPU.PCIE2_REF_PAD_CLK_P F25 - D
J5.10 DGND DGND - - G
J5.11 CSI_P2_CKN CPU.MIPI_CSI2_CLK_N A19 - D
J5.12 CSI_P2_CKP CPU.MIPI_CSI2_CLK_P B19 - D
J5.13 DGND DGND - - G
J5.14 CSI_P2_DN0 CPU.MIPI_CSI2_D0_N C20 - D
J5.15 CSI_P2_DP0 CPU.MIPI_CSI2_D0_P D10 - D
J5.16 CSI_P2_DN1 CPU.MIPI_CSI2_D1_N A20 - D
J5.17 CSI_P2_DP1 CPU.MIPI_CSI2_D1_P B20 - D
J5.18 DGND DGND - - G
J5.19 CSI_P2_DN2 CPU.MIPI_CSI2_D2_N A21 - D
J5.20 CSI_P2_DP2 CPU.MIPI_CSI2_D2_P B21 - D
J5.21 CSI_P2_DN3 CPU.MIPI_CSI2_D3_N C19 - D
J5.22 CSI_P2_DP3 CPU.MIPI_CSI2_D3_P D19 - D
J5.23 DGND DGND - - G
J5.24 I2C4_SCL CPU.I2C4_SCL F8 NVCC_3V3 I/O ALT0 I2C4_SCL
ALT1 PWM2_OUT
ALT2 PCIE1_CLKREQ_B
ALT5 GPIO5_IO20
J5.25 I2C4_SDA CPU.I2C4_SDA F9 NVCC_3V3 I/O ALT0 I2C4_SDA
ALT1 PWM1_OUT
ALT2 PCIE2_CLKREQ_B
ALT5 GPIO5_IO21
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