Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

From DAVE Developer's Wiki
Jump to: navigation, search
(→‎Introduction)
Line 15: Line 15:
 
<section end=History/>
 
<section end=History/>
 
<section begin=Body/>
 
<section begin=Body/>
−
==Pinout Table==
+
==Introduction==
−
===Introduction===
 
  
 
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.
 
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.
Line 72: Line 71:
 
|}
 
|}
  
−
===Pinout Table ODD pins declaration ===
+
==Pinout Table ODD pins declaration==
−
 
 
 
{| class="wikitable"  
 
{| class="wikitable"  
 
! latexfontsize="scriptsize" | A
 
! latexfontsize="scriptsize" | A
Line 96: Line 94:
 
|}
 
|}
  
−
===Pinout Table EVEN  pins declaration ===
+
==Pinout Table EVEN  pins declaration ==
  
 
{| class="wikitable"  
 
{| class="wikitable"  

Revision as of 16:24, 28 September 2020

HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
History
Version Issue Date Notes
1.0.0 Sep 2020 First release


Introduction[edit | edit source]

This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the Axel Ultra components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver
  • PMIC.<x> : pin connected to the Power Manager IC
  • LAN.<x> : pin connected to the LAN PHY
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Pinout Table ODD pins declaration[edit | edit source]

A B C D E F G H
A A A A A A A A A

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30 - S
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS I internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
J1.24 EXT_RESET MASTER RESET - - I internal pull-up to NVCC_SNVS
J1.26 SAI3_RXC CPU.SAI3_RXC F4 NVCC_3V3 I/O ALT0 SAI3_RX_BCLK
ALT1 GPT1_CAPTURE2
ALT2 SAI5_RX_BCLK
ALT5 GPIO4_IO29
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 R4 NVCC_3V3 I/O Internally used for SW reset, do not connect ALT0 GPIO1_IO02
ALT1 WDOG1_WDOG_B
ALT5 WDOG1_WDOG_ANY
ALT7 SJC_DE_B
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD F3 NVCC_3V3 I/O ALT0 SAI3_RX_DATA0
ALT1 GPT1_COMPARE1
ALT2 SAI5_RX_DATA0
ALT5 GPIO4_IO30
J1.34 SAI2_MCLK CPU.SAI2_MCLK H5 NVCC_3V3 I/O ALT0 SAI2_MCLK
ALT1 SAI5_MCLK
ALT5 GPIO4_IO27
J1.36 SAI3_RXFS CPU.SAI3_RXFS G4 NVCC_3V3 I/O ALT0 SAI3_RX_SYNC
ALT1 GPT1_CAPTURE1
ALT2 SAI5_RX_SYNC
ALT5 GPIO4_IO28
J1.38 I2C3_SCL CPU.I2C3_SCL G8 NVCC_3V3 I/O ALT0 I2C3_SCL
ALT1 PWM4_OUT
ALT2 GPT2_CLK
ALT5 GPIO5_IO18
J1.40 SAI3_TXFS CPU.SAI3_TXFS G3 NVCC_3V3 I/O ALT0 SAI3_TX_SYNC
ALT1 GPT1_CLK
ALT2 SAI5_RX_DATA1
ALT5 GPIO4_IO31
J1.42 SPDIF_RX CPU.SPDIF_RX G6 NVCC_3V3 I/O ALT0 SPDIF1_IN
ALT1 PWM2_OUT
ALT5 GPIO5_IO04
J1.44 SPDIF_TX CPU.SPDIF_TX F6 NVCC_3V3 I/O ALT0 SPDIF1_OUT
ALT1 PWM3_OUT
ALT5 GPIO5_IO03
J1.46 SAI3_MCLK CPU.SAI3_MCLK D3 NVCC_3V3 I/O ALT0 SAI3_MCLK
ALT1 PWM4_OUT
ALT2 SAI5_MCLK
ALT5 GPIO5_IO02
J1.48 I2C3_SDA CPU.I2C3_SDA E9 NVCC_3V3 I/O ALT0 I2C3_SDA
ALT1 PWM3_OUT
ALT2 GPT3_CLK
ALT5 GPIO5_IO19
J1.50 SAI3_TXC CPU.SAI3_TXC C4 NVCC_3V3 I/O ALT0 SAI3_TX_BCLK
ALT1 GPT1_COMPARE2
ALT2 SAI5_RX_DATA2
ALT5 GPIO5_IO00
J1.52 SAI3_TXD CPU.SAI3_TXD C3 NVCC_3V3 I/O ALT0 SAI3_TX_DATA0
ALT1 GPT1_COMPARE3
ALT2 SAI5_RX_DATA3
ALT5 GPIO5_IO01
J1.54 GPIO1_IO10 CPU.GPIO1_IO10 M7 NVCC_3V3 I/O Internally used for ETH PHY interrupt, do not connect ALT0 GPIO1_IO10
ALT1 USB1_OTG_ID
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK K4 NVCC_3V3 I/O ALT0 SAI5_MCLK
ALT1 SAI1_TX_BCLK
ALT2 SAI4_MCLK
ALT5 GPIO3_IO25
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 J6 NVCC_3V3 I/O ALT0 GPIO1_IO15
ALT1 USB2_OTG_OC
ALT5 PWM4_OUT
ALT6 CCM_CLKO2
J1.62 SAI5_RXFS CPU.SAI5_RXFS N4 NVCC_3V3 I/O ALT0 SAI5_RX_SYNC
ALT1 SAI1_TX_DATA0
ALT5 GPIO3_IO19
J1.64 SAI5_RXC CPU.SAI5_RXC L5 NVCC_3V3 I/O ALT0 SAI5_RX_BCLK
ALT1 SAI1_TX_DATA1
ALT5 GPIO3_IO20
J1.66 SAI2_TXC CPU.SAI2_TXC J5 NVCC_3V3 I/O ALT0 SAI2_TX_BCLK
ALT1 SAI5_TX_DATA2
ALT5 GPIO4_IO25
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 G5 NVCC_3V3 I/O ALT0 SAI2_TX_DATA0
ALT1 SAI5_TX_DATA3
ALT5 GPIO4_IO26
J1.70 SAI2_TXFS CPU.SAI2_TXFS H4 NVCC_3V3 I/O ALT0 SAI2_TX_SYNC
ALT1 SAI5_TX_DATA1
ALT5 GPIO4_IO24
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 H6 NVCC_3V3 I/O ALT0 SAI2_RX_DATA0
ALT1 SAI5_TX_DATA0
ALT5 GPIO4_IO23
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 M5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0
ALT1 SAI1_TX_DATA2
ALT5 GPIO3_IO21
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 L4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1
ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_SYNC
ALT5 GPIO3_IO212
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 M4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA2
ALT1 SAI1_TX_DATA4
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_BCLK
ALT5 GPIO3_IO23
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 K5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA3
ALT1 SAI1_TX_DATA5
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_DATA0
ALT5 GPIO3_IO24
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N T22 VDDA_1V8 D
J1.86 CLK2_P CPU.CLK2_P U22 VDDA_1V8 D
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N K24 VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P K25 VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N H24 VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P H25 VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N J24 VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P J25 VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N A22 - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P B22 - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N A23 - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P B23 - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N C22 - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P D22 - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N B24 - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P C23 - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N C21 - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P D21 - D
J1.122 DGND DGND - - G
J1.124

(NAND on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.124

(eMMC on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O ALT0 RAWNAND_DQS
ALT1 QSPI_A_DQS
ALT5 GPIO3_IO14
J1.126

(NAND on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.126

(eMMC on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O ALT0 RAWNAND_ALE
ALT1 QSPI_A_SCLK
ALT5 GPIO3_IO00
J1.128

(NAND on board)

SD1_CLK CPU.SD1_CLK L25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CLK
ALT5 GPIO2_IO00
J1.128

(eMMC on board)

NAND_CE0_B CPU.NAND_CE0_B H19 NVCC_3V3 I/O ALT0 RAWNAND_CE0_B
ALT1 QSPI_A_SS0_B
ALT5 GPIO3_IO01
J1.130

(NAND on board)

SD1_CMD CPU.SD1_CMD L24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CMD
ALT5 GPIO2_IO01
J1.130

(eMMC on board)

NAND_CE1_B CPU.NAND_CE1_B G21 NVCC_3V3 I/O ALT0 RAWNAND_CE1_B
ALT1 QSPI_A_SS1_B
ALT5 GPIO3_IO02
J1.132

(NAND on board)

SD1_RST_B CPU.SD1_RST_B R24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_RESET_B
ALT5 GPIO2_IO10
J1.132

(eMMC on board)

NAND_CE2_B CPU.NAND_CE2_B F21 NVCC_3V3 I/O ALT0 RAWNAND_CE2_B
ALT1 QSPI_B_SS0_B
ALT5 GPIO3_IO03
J1.134

(NAND on board)

SD1_STROBE CPU.SD1_STROBE T24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_STROBE
ALT5 GPIO2_IO11
J1.134

(eMMC on board)

NAND_CE3_B CPU.NAND_CE3_B H20 NVCC_3V3 I/O ALT0 RAWNAND_CE3_B
ALT1 QSPI_B_SS1_B
ALT5 GPIO3_IO034
J1.136

(NAND on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.136

(eMMC on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O ALT0 RAWNAND_CLE
ALT1 QSPI_B_SCLK
ALT5 GPIO3_IO05
J1.138

(NAND on board)

SD1_DATA0 CPU.SD1_DATA0 M25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA0
ALT5 GPIO2_IO02
J1.138

(eMMC on board)

NAND_DATA00 CPU.NAND_DATA00 G20 NVCC_3V3 I/O ALT0 RAWNAND_DATA00
ALT1 QSPI_A_DATA0
ALT5 GPIO3_IO06
J1.140

(NAND on board)

SD1_DATA1 CPU.SD1_DATA1 M24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA1
ALT5 GPIO2_IO0
J1.140

(eMMC on board)

NAND_DATA01 CPU.NAND_DATA01 J20 NVCC_3V3 I/O ALT0 RAWNAND_DATA01
ALT1 QSPI_A_DATA1
ALT5 GPIO3_IO07
J1.142

(NAND on board)

SD1_DATA2 CPU.SD1_DATA2 N25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA2
ALT5 GPIO2_IO04
J1.142

(eMMC on board)

NAND_DATA02 CPU.NAND_DATA02 H22 NVCC_3V3 I/O ALT0 RAWNAND_DATA02
ALT1 QSPI_A_DATA2
ALT5 GPIO3_IO08
J1.144

(NAND on board)

SD1_DATA3 CPU.SD1_DATA3 P25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA3
ALT5 GPIO2_IO05
J1.144

(eMMC on board)

NAND_DATA03 CPU.NAND_DATA03 J21 NVCC_3V3 I/O ALT0 RAWNAND_DATA03
ALT1 QSPI_A_DATA3
ALT5 GPIO3_IO09
J1.146 DGND DGND - - G
J1.148

(NAND on board)

SD1_DATA4 CPU.SD1_DATA4 N24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA4
ALT5 GPIO2_IO06
J1.148

(eMMC on board)

NAND_DATA04 CPU.NAND_DATA04 L20 NVCC_3V3 I/O ALT0 RAWNAND_DATA04
ALT1 QSPI_B_DATA0
ALT5 GPIO3_IO10
J1.150

(NAND on board)

SD1_DATA5 CPU.SD1_DATA5 P24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA5
ALT5 GPIO2_IO07
J1.150

(eMMC on board)

NAND_DATA05 CPU.NAND_DATA05 J22 NVCC_3V3 I/O ALT0 RAWNAND_DATA05
ALT1 QSPI_B_DATA1
ALT5 GPIO3_IO11
J1.152

(NAND on board)

SD1_DATA6 CPU.SD1_DATA6 R25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA6
ALT5 GPIO2_IO08
J1.152

(eMMC on board)

NAND_DATA06 CPU.NAND_DATA06 L19 NVCC_3V3 I/O ALT0 RAWNAND_DATA06
ALT1 QSPI_B_DATA2
ALT5 GPIO3_IO12
J1.154

(NAND on board)

SD1_DATA7 CPU.SD1_DATA7 T25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA7
ALT5 GPIO2_IO09
J1.154

(eMMC on board)

NAND_DATA07 CPU.NAND_DATA07 M19 NVCC_3V3 I/O ALT0 RAWNAND_DATA07
ALT1 QSPI_B_DATA3
ALT5 GPIO3_IO13
J1.156

(NAND on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.156

(eMMC on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O ALT0 RAWNAND_RE_B
ALT1 QSPI_B_DQS
ALT5 GPIO3_IO15
J1.158

(NAND on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.158

(eMMC on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O ALT0 RAWNAND_READY_B
ALT5 GPIO3_IO16
J1.160

(NAND on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.160

(eMMC on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O ALT0 RAWNAND_WE_B
ALT5 GPIO3_IO17
J1.162

(NAND on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.162

(eMMC on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O ALT0 RAWNAND_WP_B
ALT5 GPIO3_IO18
J1.164 DGND DGND - - G
J1.166 CLK1_N CPU.CLK1_N T23 D
J1.168 CLK1_P CPU.CLK1_P R23 D
J1.170 USB2_RXN CPU.USB2_RX_N B8 D
J1.172 USB2_RXP CPU.USB2_RX_P A8 D
J1.174 USB2_TXN CPU.USB2_TX_N B9 D
J1.176 USB2_TXP CPU.USB2_TX_P A9 D
J1.178 USB1_RXN CPU.USB1_RX_N B12 D
J1.180 USB1_RXP CPU.USB1_RX_P A12 D
J1.182 USB1_TXN CPU.USB1_TX_N B13 D
J1.184 USB1_TXP CPU.USB1_TX_P A13 D
J1.186 USB1_VBUS CPU.USB1_VBUS D14 - S
J1.188 USB2_VBUS CPU.USB2_VBUS D9 - S
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C14 VDD_PHY_3V3 I
J1.194 USB2_ID CPU.USB2_ID C9 VDD_PHY_3V3 I
J1.196 USB1_DN CPU.USB1_DN B14 - D
J1.198 USB1_DP CPU.USB1_DP A14 - D
J1.200 USB2_DP CPU.USB2_DP A10 - D
J1.202 USB2_DN CPU.USB2_DN B10 - D
J1.204 DGND DGND - - G

Pinout Table J4 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J4.1 DGND DGND - - G
J4.2 SAI1_RXD7 CPU.SAI1_RXD7 G1 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA7
ALT1 SAI6_MCLK
ALT2 SAI1_TX_SYNC
ALT3 SAI1_TX_DATA4
ALT4 CORESIGHT_TRACE7
ALT5 GPIO4_IO09
ALT6 SRC_BOOT_CFG7
J4.3 SAI1_RXD6 CPU.SAI1_RXD6 G2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA6
ALT1 SAI6_TX_SYNC
ALT2 SAI6_RX_SYNC
ALT4 CORESIGHT_TRACE6
ALT5 GPIO4_IO08
ALT6 SRC_BOOT_CFG6
J4.4 SAI1_RXD5 CPU.SAI1_RXD5 F1 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA5
ALT1 SAI6_TX_DATA0
ALT2 SAI6_RX_DATA0
ALT3 SAI1_RX_SYNC
ALT4 CORESIGHT_TRACE5
ALT5 GPIO4_IO07
ALT6 SRC_BOOT_CFG5
J4.5 SAI1_RXD4 CPU.SAI1_RXD4 J1 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA4
ALT1 SAI6_TX_BCLK
ALT2 SAI6_RX_BCLK
ALT4 CORESIGHT_TRACE4
ALT5 GPIO4_IO06
ALT6 SRC_BOOT_CFG4
J4.6 SAI1_RXD3 CPU.SAI1_RXD3 J2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA3
ALT1 SAI5_RX_DATA3
ALT4 CORESIGHT_TRACE3
ALT5 GPIO4_IO05
ALT6 SRC_BOOT_CFG3
J4.7 SAI1_RXD2 CPU.SAI1_RXD2 H2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA2
ALT1 SAI5_RX_DATA2
ALT4 CORESIGHT_TRACE2
ALT5 GPIO4_IO04
ALT6 SRC_BOOT_CFG2
J4.8 SAI1_RXD1 CPU.SAI1_RXD1 L2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA1
ALT1 SAI5_RX_DATA1
ALT4 CORESIGHT_TRACE1
ALT5 GPIO4_IO03
ALT6 SRC_BOOT_CFG1
J4.9 SAI1_RXD0 CPU.SAI1_RXD0 K2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_RX_DATA0
ALT1 SAI5_RX_DATA0
ALT4 CORESIGHT_TRACE0
ALT5 GPIO4_IO02
ALT6 SRC_BOOT_CFG0
J4.10 SAI1_RXC CPU.SAI1_RXC K1 NVCC_3V3 I/O ALT0 SAI1_RX_BCLK
ALT1 SAI5_RX_BCLK
ALT4 CORESIGHT_TRACE_CTL
ALT5 GPIO4_IO01
J4.11 SAI1_RXFS CPU.SAI1_RXFS L1 NVCC_3V3 I/O ALT0 SAI1_RX_SYNC
ALT1 SAI5_RX_SYNC
ALT4 CORESIGHT_TRACE_CLK
ALT5 GPIO4_IO00
J4.12 DGND DGND - - G
J4.13 SAI1_MCLK CPU.SAI1_MCLK NVCC_3V3 I/O ALT0 SAI1_MCLK
ALT1 SAI5_MCLK
ALT2 SAI1_TX_BCLK
ALT5 GPIO4_IO20
J4.14 DGND DGND - - G
J4.15 SAI1_TXFS CPU.SAI1_TXFS H4 NVCC_3V3 I/O ALT0 SAI1_TX_SYNC
ALT1 SAI5_TX_SYNC
ALT4 CORESIGHT_EVENTO
ALT5 GPIO4_IO10
J4.16 SAI1_TXC CPU.SAI1_TXC J5 NVCC_3V3 I/O ALT0 SAI1_TX_BCLK
ALT1 SAI5_TX_BCLK
ALT4 CORESIGHT_EVENTI
ALT5 GPIO4_IO11
J4.17 SAI1_TXD0 CPU.SAI1_TXD0 F2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA0
ALT1 SAI5_TX_DATA0
ALT4 CORESIGHT_TRACE8
ALT5 GPIO4_IO12
ALT6 SRC_BOOT_CFG8
J4.18 SAI1_TXD1 CPU.SAI1_TXD1 E2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA1
ALT1 SAI5_TX_DATA1
ALT4 CORESIGHT_TRACE9
ALT5 GPIO4_IO13
ALT6 SRC_BOOT_CFG9
J4.19 SAI1_TXD2 CPU.SAI1_TXD2 B2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA2
ALT1 SAI5_TX_DATA2
ALT4 CORESIGHT_TRACE10
ALT5 GPIO4_IO14
ALT6 SRC_BOOT_CFG10
J4.20 SAI1_TXD3 CPU.SAI1_TXD3 D1 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA3
ALT1 SAI5_TX_DATA3
ALT4 CORESIGHT_TRACE11
ALT5 GPIO4_IO15
ALT6 SRC_BOOT_CFG11
J4.21 SAI1_TXD4 CPU.SAI1_TXD4 D2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA4
ALT1 SAI6_RX_BCLK
ALT2 SAI6_TX_BCLK
ALT4 CORESIGHT_TRACE12
ALT5 GPIO4_IO16
ALT6 SRC_BOOT_CFG12
J4.22 SAI1_TXD5 CPU.SAI1_TXD5 C2 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA5
ALT1 SAI6_RX_DATA0
ALT2 SAI6_TX_DATA0
ALT4 CORESIGHT_TRACE13
ALT5 GPIO4_IO17
ALT6 SRC_BOOT_CFG13
J4.23 SAI1_TXD6 CPU.SAI1_TXD6 B3 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA6
ALT1 SAI6_RX_SYNC
ALT2 SAI6_TX_SYNC
ALT4 CORESIGHT_TRACE14
ALT5 GPIO4_IO18
ALT6 SRC_BOOT_CFG14
J4.24 SAI1_TXD7 CPU.SAI1_TXD7 C1 NVCC_3V3 I/O internally used for BOOT config ALT0 SAI1_TX_DATA7
ALT1 SAI6_MCLK
ALT4 CORESIGHT_TRACE15
ALT5 GPIO4_IO19
ALT6 SRC_BOOT_CFG15
J4.25 DGND DGND - - G

Pinout Table J5 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J5.1 DGND DGND - - G
J5.2 PCIE2_RXN CPU.PCIE2_RXN_N D24 - D
J5.3 PCIE2_RXP CPU.PCIE2_RXN_P D25 - D
J5.4 DGND DGND - - G
J5.5 PCIE2_TXN CPU.PCIE2_TXN_N E24 - D
J5.6 PCIE2_TXP CPU.PCIE2_TXN_P E25 - D
J5.7 DGND DGND - - G
J5.8 PCIE2_REF_CLKN CPU.PCIE2_REF_PAD_CLK_N F24 - D
J5.9 PCIE2_REF_CLKP CPU.PCIE2_REF_PAD_CLK_P F25 - D
J5.10 DGND DGND - - G
J5.11 CSI_P2_CKN CPU.MIPI_CSI2_CLK_N A19 - D
J5.12 CSI_P2_CKP CPU.MIPI_CSI2_CLK_P B19 - D
J5.13 DGND DGND - - G
J5.14 CSI_P2_DN0 CPU.MIPI_CSI2_D0_N C20 - D
J5.15 CSI_P2_DP0 CPU.MIPI_CSI2_D0_P D10 - D
J5.16 CSI_P2_DN1 CPU.MIPI_CSI2_D1_N A20 - D
J5.17 CSI_P2_DP1 CPU.MIPI_CSI2_D1_P B20 - D
J5.18 DGND DGND - - G
J5.19 CSI_P2_DN2 CPU.MIPI_CSI2_D2_N A21 - D
J5.20 CSI_P2_DP2 CPU.MIPI_CSI2_D2_P B21 - D
J5.21 CSI_P2_DN3 CPU.MIPI_CSI2_D3_N C19 - D
J5.22 CSI_P2_DP3 CPU.MIPI_CSI2_D3_P D19 - D
J5.23 DGND DGND - - G
J5.24 I2C4_SCL CPU.I2C4_SCL F8 NVCC_3V3 I/O ALT0 I2C4_SCL
ALT1 PWM2_OUT
ALT2 PCIE1_CLKREQ_B
ALT5 GPIO5_IO20
J5.25 I2C4_SDA CPU.I2C4_SDA F9 NVCC_3V3 I/O ALT0 I2C4_SDA
ALT1 PWM1_OUT
ALT2 PCIE2_CLKREQ_B
ALT5 GPIO5_IO21

Pinout Table JD5 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
JD5.1 DGND DGND - - G
JD5.2 EEPROM_WP Internal EEPROM Write Protect - NVCC_3V3 I
JD5.3 NC Not Connected - - Z
JD5.4 JTAG_TCK CPU.JTAG_TCK T5 NVCC_3V3 I internal pull-up 10k to NVCC_3V3
JD5.5 JTAG_TMS CPU.JTAG_TMS V5 NVCC_3V3 I
JD5.6 JTAG_TDO CPU.JTAG_TDO U5 NVCC_3V3 O
JD5.7 JTAG_TDI CPU.JTAG_TDI W5 NVCC_3V3 I
JD5.8 JTAG_nTRST CPU.JTAG_TRST_B U6 NVCC_3V3 I
JD5.9 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
JD5.10 NVCC_3V3 NVCC_3V3 - - S
HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
Retrieved from "https://wiki.dave.eu/index.php?title=MITO_8M_SOM/MITO_8M_Hardware/Pinout_Table&oldid=10301"