Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Peripherals/UARTs"
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==Peripheral UARTs == | ==Peripheral UARTs == | ||
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=== Description === | === Description === | ||
| − | The | + | The Universal Asynchronous Receiver/Transmitter (UART) interface available on MITO 8M is based on iMX8M SoC. |
| − | + | UARTs provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format. | |
| − | * High- | + | The UART port supports the following standards and features: |
| − | * | + | * High-speed TIA/EIA-232-F compatible, up to Mbit/s |
| − | * | + | * Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s) |
| − | * | + | * 9-bit or Multidrop mode (RS-485) support (automatic slave address detection) |
| + | * 7 or 8 data bits for RS-232 characters, or 9 bit RS-485 format | ||
| + | * 1 or 2 stop bits | ||
| + | * Programmable parity (even, odd, and no parity) | ||
| + | * Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals | ||
| + | * Two independent, 32-entry FIFOs for transmit and receive | ||
===Pin mapping=== | ===Pin mapping=== | ||
Latest revision as of 17:55, 28 December 2023
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| History | |||
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| Issue Date | Notes | ||
| 2020/10/27 | First release | ||
Peripheral UARTs[edit | edit source]
Description[edit | edit source]
The Universal Asynchronous Receiver/Transmitter (UART) interface available on MITO 8M is based on iMX8M SoC.
UARTs provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format.
The UART port supports the following standards and features:
- High-speed TIA/EIA-232-F compatible, up to Mbit/s
- Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
- 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)
- 7 or 8 data bits for RS-232 characters, or 9 bit RS-485 format
- 1 or 2 stop bits
- Programmable parity (even, odd, and no parity)
- Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals
- Two independent, 32-entry FIFOs for transmit and receive
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
