Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Peripherals/SPI"
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Latest revision as of 17:54, 28 December 2023
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| History | |||
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| 2020/10/27 | First release | ||
Peripheral SPI[edit | edit source]
The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex, synchronous, four-wire serial communication block.
Description[edit | edit source]
Three SPI interface are available on MITO 8M based on iMX8M SoC.
The SPI port supports the following standards and features:
- Full-duplex synchronous serial interface
- Master/Slave configurable
- One Chip Select (SS) signal
- Transfer continuation function allows unlimited length data transfers
- 32-bit wide by 64-entry FIFO for both transmit and receive data
- Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
- Direct Memory Access (DMA) support
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
