Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Peripherals/LVDS"
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| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0 |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release |
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==Peripheral LVDS == | ==Peripheral LVDS == | ||
| − | + | The LVDS interface available on MITO 8M is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC. | |
| − | + | ||
| + | It is directly connected to the MIPI® DSI output port of iMX8M SOC. | ||
| + | |||
| + | This support covers all aspects of these activities: | ||
| + | * Connectivity to relevant devices - Displays with LVDS receivers | ||
| + | * Arranging the data as required by the external display receiver and by LVDS display standards | ||
| + | * Synchronization and control capabilities | ||
=== Description === | === Description === | ||
| − | |||
| − | |||
The LVDS port supports the following standards and features: | The LVDS port supports the following standards and features: | ||
| − | * | + | * Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp |
| − | + | * Output Configurable for Single-Link or Dual-Link LVDS | |
| − | * | + | * LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes |
| − | * | ||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 07:30, 2 October 2020
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| Version | Issue Date | Notes | |
| 1.0.0 | Oct 2020 | First release | |
Peripheral LVDS[edit | edit source]
The LVDS interface available on MITO 8M is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC.
It is directly connected to the MIPI® DSI output port of iMX8M SOC.
This support covers all aspects of these activities:
- Connectivity to relevant devices - Displays with LVDS receivers
- Arranging the data as required by the external display receiver and by LVDS display standards
- Synchronization and control capabilities
Description[edit | edit source]
The LVDS port supports the following standards and features:
- Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
- Output Configurable for Single-Link or Dual-Link LVDS
- LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
