Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem"
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{| class="wikitable" | | {| class="wikitable" | | ||
| align="center" style="background:#f0f0f0;" |'''Processor''' | | align="center" style="background:#f0f0f0;" |'''Processor''' | ||
| − | | align="center" style="background:#f0f0f0;" |''' | + | | align="center" style="background:#f0f0f0;" |'''i.MX8M Dual''' |
| − | + | |'''i.MX8M Quad''' | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|- | |- | ||
| − | | | + | |# Cores |
| − | 1x Arm® Cortex®-M4 | + | |2x Arm® Cortex®-A53 |
| − | | | + | 1x Arm® Cortex®-M4 |
| − | 1.5 GHz | + | |4x Arm® Cortex®-A53 |
| − | | | + | 1x Arm® Cortex®-M4 |
| − | (LPDDR4-3200) | + | |- |
| − | | | + | |Clock|| colspan="2" |1.3 GHz |
| − | + | 1.5 GHz | |
| − | + | |- | |
| − | + | |L2 | |
| − | | | + | Cache |
| − | + | | colspan="2" |1 MB | |
| + | |- | ||
| + | |LPDDR4 | ||
| + | | colspan="2" |32 bit @ 1600 MHz | ||
| + | (LPDDR4-3200) | ||
| + | |- | ||
| + | |GPU | ||
| + | | colspan="2" |4 Shader | ||
| + | OpenGL ES 1.1, 2.0, 3.0, 3.1 | ||
| + | Open CL 1.2 | ||
| + | Vulkan | ||
| + | |- | ||
| + | |VPU | ||
| + | | colspan="2" |4Kp60 HEVC/H.265 main, and main 10 decoder | ||
4Kp60 VP9 decoder | 4Kp60 VP9 decoder | ||
| − | |||
4Kp30 AVC/H.264 decoder | 4Kp30 AVC/H.264 decoder | ||
| − | |||
1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder | 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder | ||
| − | + | |- | |
| − | | | + | |Display |
| + | Controller | ||
| + | | colspan="2" |Dual Independent | ||
Display Support | Display Support | ||
| − | + | up tp 4kp60 | |
| − | up tp 4kp60 | + | |- |
| − | | | + | |Video |
| + | Output | ||
| + | | colspan="2" |1x HDMI 2.0a | ||
1x MIPI-DSI | 1x MIPI-DSI | ||
| − | |||
(with MIPI to LVDS bridge) | (with MIPI to LVDS bridge) | ||
| − | | | + | |- |
| + | |Camera | ||
| + | Input | ||
| + | | colspan="2" |2x MIPI CSI | ||
(4-lanes each) | (4-lanes each) | ||
| − | | | + | |- |
| + | |PCIe | ||
| + | | colspan="2" |2x PCIe 2.0 | ||
(1-lane each) | (1-lane each) | ||
| − | | | + | |- |
| + | |USB | ||
| + | | colspan="2" |2x USB 3.0 | ||
Dual role | Dual role | ||
| − | |||
| − | |||
| − | |||
|- | |- | ||
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison | ||
Revision as of 11:43, 29 September 2020
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
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| Version | Issue Date | Notes | |
| 1.0.0 | Sep 2020 | First release | |
TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)
Contents
Processor and memory subsystem[edit | edit source]
The heart of MITO 8M module is composed by the following components:
- i.MX8M SoC application processor
- Power supply unit
- LPDDR4 memory bank
- eMMC or NAND flash banks
- Connectors:
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
- partially compatible with AXEL Lite SOM
- 2 x 25 pins One Piece mating board layout Expansion
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main MITO 8M components.
Processor Info[edit | edit source]
| Processor | i.MX8M Dual | i.MX8M Quad |
| # Cores | 2x Arm® Cortex®-A53
1x Arm® Cortex®-M4 |
4x Arm® Cortex®-A53
1x Arm® Cortex®-M4 |
| Clock | 1.3 GHz
1.5 GHz | |
| L2
Cache |
1 MB | |
| LPDDR4 | 32 bit @ 1600 MHz
(LPDDR4-3200) | |
| GPU | 4 Shader
OpenGL ES 1.1, 2.0, 3.0, 3.1 Open CL 1.2 Vulkan | |
| VPU | 4Kp60 HEVC/H.265 main, and main 10 decoder
4Kp60 VP9 decoder 4Kp30 AVC/H.264 decoder 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder | |
| Display
Controller |
Dual Independent
Display Support up tp 4kp60 | |
| Video
Output |
1x HDMI 2.0a
1x MIPI-DSI (with MIPI to LVDS bridge) | |
| Camera
Input |
2x MIPI CSI
(4-lanes each) | |
| PCIe | 2x PCIe 2.0
(1-lane each) | |
| USB | 2x USB 3.0
Dual role | |
RAM memory bank[edit | edit source]
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
| CPU connection | Multi-mode DDR controller (MMDC) |
| Size max | 4 GB |
| Width | 32 bit |
| Speed | 1600 MHz |
eMMC flash bank[edit | edit source]
On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
| CPU connection | SDIO1 |
| Size min | 4 GB |
| Size max | 64 GB |
| Bootable | Yes |
NAND flash bank[edit | edit source]
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
| CPU connection | Raw NAND flash controller |
| Page size | TBD |
| Size min | TBD |
| Size max | TBD |
| Width | 8 bit |
| Chip select | TBD |
| Bootable | Yes |
Memory map[edit | edit source]
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.
Power supply unit[edit | edit source]
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
