Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem"

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| align="center" style="background:#f0f0f0;" |'''USB'''
 
| align="center" style="background:#f0f0f0;" |'''USB'''
 
|-
 
|-
−
| i.MX8M Dual || 2 x Arm® Cortex®-A53  
+
| i.MX8M Dual || 2x Arm® Cortex®-A53  
−
1 x Arm® Cortex®-M4  
+
1x Arm® Cortex®-M4  
 
| rowspan="2" |1.3 GHz
 
| rowspan="2" |1.3 GHz
 
1.5 GHz  
 
1.5 GHz  
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up tp 4kp60  
 
up tp 4kp60  
−
| rowspan="2" |1 x HDMI 2.0a
+
| rowspan="2" |1x HDMI 2.0a
−
1 x MIPI-DSI
+
1x MIPI-DSI
  
 
(with MIPI to LVDS bridge)
 
(with MIPI to LVDS bridge)
−
| rowspan="2" |2 x MIPI CSI
+
| rowspan="2" |2x MIPI CSI
 
(4-lanes each)
 
(4-lanes each)
−
| rowspan="2" | 2 x PCIe 2.0
+
| rowspan="2" | 2x PCIe 2.0
 
(1-lane each)
 
(1-lane each)
−
| rowspan="2" |2 x USB 3.0
+
| rowspan="2" |2x USB 3.0
 
Dual role
 
Dual role
 
|-
 
|-
−
| i.MX8M Quad || 4 x Arm® Cortex®-A53  
+
| i.MX8M Quad || 4x Arm® Cortex®-A53  
−
1 x Arm® Cortex®-M4  
+
1x Arm® Cortex®-M4  
 
|-
 
|-
 
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
 
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
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=== RAM memory bank ===
 
=== RAM memory bank ===
  
−
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:
+
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
 
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
 
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
−
|-
 
−
| '''Size min'''||512 MB
 
 
|-
 
|-
 
| '''Size max'''||4 GB  
 
| '''Size max'''||4 GB  
 
|-
 
|-
−
| '''Width'''||64 bit  
+
| '''Width'''||32 bit  
 
|-
 
|-
−
| '''Speed'''||533 MHz  
+
| '''Speed'''||1600 MHz  
 
|-
 
|-
 
|}
 
|}
  
−
=== NOR flash bank ===
+
=== eMMC flash bank ===
  
−
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:
+
On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''||eCSPI channel 5
+
| '''CPU connection'''||SDIO1
 
|-
 
|-
−
| '''Size min'''||8 MB
+
| '''Size min'''||4 GB
 
|-
 
|-
−
| '''Size max'''||64 MB
+
| '''Size max'''||64 GB
−
|-
 
−
| '''Chip select'''||ECSPI5_SS0
 
 
|-
 
|-
 
| '''Bootable'''||Yes
 
| '''Bootable'''||Yes
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=== NAND flash bank ===
 
=== NAND flash bank ===
  
−
On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
+
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
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| '''CPU connection'''||Raw NAND flash controller
 
| '''CPU connection'''||Raw NAND flash controller
 
|-
 
|-
−
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
+
| '''Page size'''|| TBD
 
|-
 
|-
−
| '''Size min'''||128 MB
+
| '''Size min'''||TBD
 
|-
 
|-
−
| '''Size max'''||2 GB
+
| '''Size max'''||TBD
 
|-
 
|-
 
| '''Width'''||8 bit  
 
| '''Width'''||8 bit  
 
|-
 
|-
−
| '''Chip select'''||NANDF_CS0
+
| '''Chip select'''||TBD
−
|-
 
−
| '''Bootable'''||Yes
 
−
|-
 
−
|}
 
−
 
 
−
=== eMMC flash bank ===
 
−
 
 
−
{| class="wikitable" |
 
−
|-
 
−
| '''CPU connection'''|| SDIO
 
−
|-
 
−
| '''Page size'''|| xxxxxx
 
−
|-
 
−
| '''Size min'''||xxx MB
 
−
|-
 
−
| '''Size max'''||xxx GB
 
−
|-
 
−
| '''Width'''|| xx bit
 
−
|-
 
−
| '''SDHC'''||
 
 
|-
 
|-
 
| '''Bootable'''||Yes  
 
| '''Bootable'''||Yes  
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MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
 
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
−
 
  
 
----
 
----
  
 
[[Category:MITO 8M]]
 
[[Category:MITO 8M]]

Revision as of 14:18, 23 September 2020

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History
Version Issue Date Notes
1.0.0 Sep 2020 First release


TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)

Processor and memory subsystem[edit | edit source]

The heart of MITO 8M module is composed by the following components:

  • i.MX8M SoC application processor
  • Power supply unit
  • LPDDR4 memory bank
  • eMMC or NAND flash banks
  • Connectors:
    • 1 x 204 pins SO-DIMM edge connector with interfaces signals
    • 2 x 25 pins One Piece mating board layout Expansion

This chapter shortly describes the main MITO 8M components.

Processor Info[edit | edit source]

Processor # Cores Clock L2

Cache

LPDDR4 GPU VPU Display

Controller

Video

Output

Camera

Input

PCIe USB
i.MX8M Dual 2x Arm® Cortex®-A53

1x Arm® Cortex®-M4

1.3 GHz

1.5 GHz

1 MB 32 bit @ 1600 MHz

(LPDDR4-3200)

4 Shader
  • OpenGL ES 1.1, 2.0, 3.0, 3.1
  • Open CL 1.2
  • Vulkan
 4Kp60 HEVC/H.265 main, and main 10 decoder

4Kp60 VP9 decoder

4Kp30 AVC/H.264 decoder

1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder

Dual Independent

Display Support

up tp 4kp60

1x HDMI 2.0a

1x MIPI-DSI

(with MIPI to LVDS bridge)

2x MIPI CSI

(4-lanes each)

2x PCIe 2.0

(1-lane each)

2x USB 3.0

Dual role

i.MX8M Quad 4x Arm® Cortex®-A53

1x Arm® Cortex®-M4

Table: i.MX8M models comparison

RAM memory bank[edit | edit source]

LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:

CPU connection Multi-mode DDR controller (MMDC)
Size max 4 GB
Width 32 bit
Speed 1600 MHz

eMMC flash bank[edit | edit source]

On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection SDIO1
Size min 4 GB
Size max 64 GB
Bootable Yes

NAND flash bank[edit | edit source]

Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:

CPU connection Raw NAND flash controller
Page size TBD
Size min TBD
Size max TBD
Width 8 bit
Chip select TBD
Bootable Yes

Memory map[edit | edit source]

For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.

Power supply unit[edit | edit source]

MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.

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Roadmap IoT Services ML/AI services Embedded Design Services
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