Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem"

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<section end=History/>
 
<section end=History/>
 
<section begin=Body/>
 
<section begin=Body/>
−
 
−
''TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)''
 
  
 
== Processor and memory subsystem ==
 
== Processor and memory subsystem ==
  
 
The heart of MITO 8M module is composed by the following components:
 
The heart of MITO 8M module is composed by the following components:
−
* ''TBD: SOC name'' SoC application processor
+
*i.MX8M SoC application processor
 
* Power supply unit
 
* Power supply unit
−
* DDR memory banks
+
* LPDDR4 memory bank
−
* NOR and NAND flash banks
+
* eMMC or NAND flash banks
−
* ''TBD: SOM connector type'' connector with interfaces signals
+
* Connectors:
 +
** 1 x 204 pins SO-DIMM edge connector with interfaces signals
 +
*** partially compatible with [[AXEL Lite SOM]]
 +
** 2 x 25 pins One Piece mating board layout Expansion
  
−
This chapter shortly describes the main Axel Lite components.
+
This chapter shortly describes the main MITO 8M components.
  
 
=== Processor Info ===
 
=== Processor Info ===
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
−
| align="center" style="background:#f0f0f0;"|'''Processor'''
+
| align="center" style="background:#f0f0f0;" |'''Processor'''
−
| align="center" style="background:#f0f0f0;"|'''# Cores'''
+
| align="center" style="background:#f0f0f0;" |'''i.MX8M Dual'''
−
| align="center" style="background:#f0f0f0;"|'''Clock'''
+
| align="center" style="background:#f0f0f0;" |'''i.MX8M Quad'''
−
| align="center" style="background:#f0f0f0;"|'''L2 Cache'''
 
−
| align="center" style="background:#f0f0f0;"|'''DDR3'''
 
−
| align="center" style="background:#f0f0f0;"|'''Graphics Acceleration'''
 
−
| align="center" style="background:#f0f0f0;"|'''IPU'''
 
−
| align="center" style="background:#f0f0f0;"|'''VPU'''
 
−
| align="center" style="background:#f0f0f0;"|'''SATA-II'''
 
 
|-
 
|-
−
| i.MX6 Solo || 1 ||800 MHz<br>1 GHz ||512 KB ||32 bit @ 400 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. ||1x ||1x ||N.A.
+
|# Cores
 +
|2x Arm® Cortex®-A53
 +
1x Arm® Cortex®-M4
 +
|4x Arm® Cortex®-A53
 +
1x Arm® Cortex®-M4
 
|-
 
|-
−
| i.MX6 Dual || 2 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
+
|Clock|| colspan="2" |1.3 GHz  
 +
1.5 GHz
 
|-
 
|-
−
| i.MX6 Quad || 4 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
+
|L2
 +
Cache
 +
| colspan="2" |1 MB
 
|-
 
|-
−
|+ align="bottom" style="caption-side: bottom" | Table: i.MX6 models comparison
+
|LPDDR4
−
|}
+
| colspan="2" |32 bit @ 1600 MHz
−
 
+
(LPDDR4-3200)
−
=== RAM memory bank ===
+
|-
 +
|GPU
 +
| colspan="2" |4 Shader
 +
OpenGL ES 1.1, 2.0, 3.0, 3.1
 +
Open CL 1.2
 +
Vulkan
 +
|-
 +
|VPU
 +
| colspan="2" |4Kp60 HEVC/H.265 main, and main 10 decoder
 +
4Kp60 VP9 decoder
  
−
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:
+
4Kp30 AVC/H.264 decoder
  
−
{| class="wikitable" |
+
1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
 
|-
 
|-
−
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
+
|Display
 +
Controller
 +
| colspan="2" |Dual Independent
 +
Display Support
 +
up tp 4kp60
 
|-
 
|-
−
| '''Size min'''||512 MB
+
|Video
 +
Output
 +
| colspan="2" |1x HDMI 2.0a
 +
1x MIPI-DSI
 +
(with MIPI to LVDS bridge)
 
|-
 
|-
−
| '''Size max'''||4 GB
+
|Camera
 +
Input
 +
| colspan="2" |2x MIPI CSI
 +
(4-lanes each)
 
|-
 
|-
−
| '''Width'''||64 bit
+
|PCIe
 +
| colspan="2" |2x PCIe 2.0
 +
(1-lane each)
 
|-
 
|-
−
| '''Speed'''||533 MHz
+
|USB
 +
| colspan="2" |2x USB 3.0
 +
Dual role
 
|-
 
|-
 +
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
 
|}
 
|}
  
−
=== NOR flash bank ===
+
=== RAM memory bank ===
  
−
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:
+
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''||eCSPI channel 5
+
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
 
|-
 
|-
−
| '''Size min'''||8 MB
+
| '''Size max'''||4 GB
−
|-
 
−
| '''Size max'''||64 MB
 
 
|-
 
|-
−
| '''Chip select'''||ECSPI5_SS0
+
| '''Width'''||32 bit
 
|-
 
|-
−
| '''Bootable'''||Yes
+
| '''Speed'''||1600 MHz
 
|-
 
|-
 
|}
 
|}
  
−
=== NAND flash bank ===
+
=== eMMC flash bank ===
  
−
On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
+
On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''||Raw NAND flash controller
+
| '''CPU connection'''||SDIO1
 
|-
 
|-
−
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
+
| '''Size min'''||4 GB
 
|-
 
|-
−
| '''Size min'''||128 MB
+
| '''Size max'''||64 GB
 
|-
 
|-
−
| '''Size max'''||2 GB
+
| '''Bootable'''||Yes
−
|-
 
−
| '''Width'''||8 bit
 
−
|-
 
−
| '''Chip select'''||NANDF_CS0
 
−
|-
 
−
| '''Bootable'''||Yes  
 
 
|-
 
|-
 
|}
 
|}
  
−
=== eMMC flash bank ===
+
=== NAND flash bank ===
 +
{| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"
 +
| [[File:TBD.png|30px]]
 +
| '''Section not completed yet'''
 +
|}
 +
 
  
 +
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''|| SDIO
+
| '''CPU connection'''||Raw NAND flash controller
 
|-
 
|-
−
| '''Page size'''|| xxxxxx
+
| '''Page size'''|| TBD
 
|-
 
|-
−
| '''Size min'''||xxx MB
+
| '''Size min'''||TBD
 
|-
 
|-
−
| '''Size max'''||xxx GB
+
| '''Size max'''||TBD
 
|-
 
|-
−
| '''Width'''|| xx bit  
+
| '''Width'''||8 bit  
 
|-
 
|-
−
| '''SDHC'''||
+
| '''Chip select'''||TBD
 
|-
 
|-
 
| '''Bootable'''||Yes  
 
| '''Bootable'''||Yes  
 
|-
 
|-
 
|}
 
|}
−
 
  
 
=== Memory map ===
 
=== Memory map ===
  
−
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.
+
For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM i.MX8M Applications Processor Reference Manual]
  
 
=== Power supply unit ===
 
=== Power supply unit ===
  
 
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
 
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
−
 
  
 
----
 
----
  
 
[[Category:MITO 8M]]
 
[[Category:MITO 8M]]

Latest revision as of 17:46, 28 December 2023

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History
Issue Date Notes
2020/09/29 First release


Processor and memory subsystem[edit | edit source]

The heart of MITO 8M module is composed by the following components:

  • i.MX8M SoC application processor
  • Power supply unit
  • LPDDR4 memory bank
  • eMMC or NAND flash banks
  • Connectors:
    • 1 x 204 pins SO-DIMM edge connector with interfaces signals
    • 2 x 25 pins One Piece mating board layout Expansion

This chapter shortly describes the main MITO 8M components.

Processor Info[edit | edit source]

Processor i.MX8M Dual i.MX8M Quad
# Cores 2x Arm® Cortex®-A53

1x Arm® Cortex®-M4

4x Arm® Cortex®-A53

1x Arm® Cortex®-M4

Clock 1.3 GHz

1.5 GHz

L2

Cache

1 MB
LPDDR4 32 bit @ 1600 MHz

(LPDDR4-3200)

GPU 4 Shader

OpenGL ES 1.1, 2.0, 3.0, 3.1 Open CL 1.2 Vulkan

VPU 4Kp60 HEVC/H.265 main, and main 10 decoder

4Kp60 VP9 decoder

4Kp30 AVC/H.264 decoder

1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder

Display

Controller

Dual Independent

Display Support up tp 4kp60

Video

Output

1x HDMI 2.0a

1x MIPI-DSI (with MIPI to LVDS bridge)

Camera

Input

2x MIPI CSI

(4-lanes each)

PCIe 2x PCIe 2.0

(1-lane each)

USB 2x USB 3.0

Dual role

Table: i.MX8M models comparison

RAM memory bank[edit | edit source]

LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:

CPU connection Multi-mode DDR controller (MMDC)
Size max 4 GB
Width 32 bit
Speed 1600 MHz

eMMC flash bank[edit | edit source]

On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection SDIO1
Size min 4 GB
Size max 64 GB
Bootable Yes

NAND flash bank[edit | edit source]

TBD.png Section not completed yet


Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:

CPU connection Raw NAND flash controller
Page size TBD
Size min TBD
Size max TBD
Width 8 bit
Chip select TBD
Bootable Yes

Memory map[edit | edit source]

For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX8M Applications Processor Reference Manual

Power supply unit[edit | edit source]

MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.

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