MITO 8M Mini SOM/MITO 8M Mini Hardware/Power and Reset/Reset scheme and control signals
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Contents
Reset scheme and control signalsEdit
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
NVCC_VSNVS_1V8Edit
Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS_1V8.
Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.
CPU_PORnEdit
PMIC can assert this active-low signal and it is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8.
Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.
PMIC_PWRONEdit
PMIC_PWRON is internally pulled-up with a 100kΩ to VIN and has a capacitor of 10nF to GND. This input signal is connected directly to the PWRON input of the PMIC.
CPU_ONOFFEdit
CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. This input signal is connected directly to the ONOFF input of the CPU.
BOARD_PGOODEdit
BOARD_PGOOD is directly related to the internal NVCC_3V3 rail (I/O pins supply) presence and must be used as power enable for all the electronics on MITO 8M carrier board.
When the I/O pins power rail on MITO 8M Mini/Nano is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in order to avoid back-powering or other issue related to a wrong power-up sequence.
BOOT_MODE_SELEdit
BOOT_MODE_SEL is internally pulled-up with a 100kΩ to NVCC_3V3.
When connected to GND, select the external microSD as the boot device.
Handling CPU-initiated software resetEdit
By default, MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly.
For these reasons it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in DESK-MX8. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT to assert the WDOG_B signal. This signal in turn is routed to the GPIO1_IO02 pad. At the hardware level, this signal is AC-coupled to the master reset pin of the internal supervisor IC. It acts as a complete hardware reset by the assertion of its RESETn output (on the same way of EXT_RESET pin).