Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
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== Power Supply Unit (PSU) and recommended power-up sequence == | == Power Supply Unit (PSU) and recommended power-up sequence == | ||
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MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | ||
| − | [[File: | + | [[File:Mito8MMini-power-sequence.png|500x500px]] |
The PSU is composed of two main blocks: | The PSU is composed of two main blocks: | ||
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# SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason) | # SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason) | ||
# CPU_PORn (active-low) is driven low by PMIC | # CPU_PORn (active-low) is driven low by PMIC | ||
| − | # RTC_RESET_B are internally released after | + | # RTC_RESET_B are internally released after 10ms |
| − | + | # PMIC initiates power-up sequence needed by iMX8M Mini processor | |
| − | # PMIC initiates power-up sequence needed by iMX8M processor | + | # BOARD_PGOOD goes up when all CPU I/O power rail is ready |
| − | # BOARD_PGOOD goes up when | ||
# CPU_PORn is deasserted after the last regulator to bring the processor out of reset | # CPU_PORn is deasserted after the last regulator to bring the processor out of reset | ||
Revision as of 16:01, 27 January 2021
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Contents
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for iMX8M Mini/Nano processors is not a trivial task because several power rails are involved.
MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit
- additional generic power management circuitry that completes PMIC functionalities
The PSU:
- generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- 3.3VIN main power supply rail is powered
- SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- CPU_PORn (active-low) is driven low by PMIC
- RTC_RESET_B are internally released after 10ms
- PMIC initiates power-up sequence needed by iMX8M Mini processor
- BOARD_PGOOD goes up when all CPU I/O power rail is ready
- CPU_PORn is deasserted after the last regulator to bring the processor out of reset
Note on BOARD_PGOOD usage[edit | edit source]
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating.
In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution.
Additionally, we suggest using an IC with Schmitt trigger input ports.
