Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table"

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(→‎SODIMM J1 EVEN pins declaration)
(→‎SODIMM J1 EVEN pins declaration)
Line 1,709: Line 1,709:
 
|PMIC_LICELL  
 
|PMIC_LICELL  
 
|PMIC.LICELL
 
|PMIC.LICELL
−
|30
+
|46
 
| -
 
| -
 
|S
 
|S
Line 1,719: Line 1,719:
 
|CPU_ONOFF
 
|CPU_ONOFF
 
|CPU.ONOFF
 
|CPU.ONOFF
−
|W21
+
|A25
−
|NVCC_SNVS
+
|NVCC_SNVS_1V8
 
|I
 
|I
−
|internal pull-up 100k to NVCC_SNVS
+
|internal pull-up 100k to NVCC_SNVS_1V8
 
|
 
|
 
|
 
|
Line 1,749: Line 1,749:
 
|CPU_PORn
 
|CPU_PORn
 
|CPU.POR_B
 
|CPU.POR_B
−
PMIC.RESETMCU
+
PMIC.RESET_MCU
−
|W20
+
|B24
−
3
+
21
−
|NVCC_SNVS
+
|NVCC_SNVS_1V8
 
|I/O
 
|I/O
−
|internal pull-up 100k to NVCC_SNVS
+
|internal pull-up 100k to NVCC_SNVS_1V8
 
|
 
|
 
|
 
|
 
|-
 
|-
 
|J1.24
 
|J1.24
−
|EXT_RESET
+
|PMIC_PWRON
−
|MASTER RESET
+
|PMIC.PWRON
−
| -
+
| 22
 
| -
 
| -
 
|I
 
|I
−
|internal pull-up to NVCC_SNVS
+
|internal pull-up 100k to VIN
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="4" |J1.26
+
| rowspan="5" |J1.26
−
| rowspan="4" |SAI3_RXC
+
| rowspan="5" |SAI3_RXC
−
| rowspan="4" |CPU.SAI3_RXC
+
| rowspan="5" |CPU.SAI3_RXC
−
| rowspan="4" |F4
+
| rowspan="5" |AG7
−
| rowspan="4" |NVCC_3V3
+
| rowspan="5" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="5" |I/O
−
| rowspan="4" |
+
| rowspan="5" |
 
|ALT0
 
|ALT0
 
|SAI3_RX_BCLK
 
|SAI3_RX_BCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|GPT1_CAPTURE2
+
|GPT1_CLK
 
|-
 
|-
 
|ALT2
 
|ALT2
 
|SAI5_RX_BCLK
 
|SAI5_RX_BCLK
 +
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)
 +
|-
 +
|ALT4
 +
|UART2_CTS_B
 
|-
 
|-
 
|ALT5
 
|ALT5
Line 1,790: Line 1,794:
 
| rowspan="4" |GPIO1_IO02
 
| rowspan="4" |GPIO1_IO02
 
| rowspan="4" |CPU.GPIO1_IO02
 
| rowspan="4" |CPU.GPIO1_IO02
−
| rowspan="4" |R4
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,819: Line 1,823:
 
| rowspan="4" |SAI3_RXD
 
| rowspan="4" |SAI3_RXD
 
| rowspan="4" |CPU.SAI3_RXD
 
| rowspan="4" |CPU.SAI3_RXD
−
| rowspan="4" |F3
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,838: Line 1,842:
 
| rowspan="3" |SAI2_MCLK
 
| rowspan="3" |SAI2_MCLK
 
| rowspan="3" |CPU.SAI2_MCLK
 
| rowspan="3" |CPU.SAI2_MCLK
−
| rowspan="3" |H5
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 1,854: Line 1,858:
 
| rowspan="4" |SAI3_RXFS
 
| rowspan="4" |SAI3_RXFS
 
| rowspan="4" |CPU.SAI3_RXFS
 
| rowspan="4" |CPU.SAI3_RXFS
−
| rowspan="4" |G4
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,873: Line 1,877:
 
| rowspan="4" |I2C3_SCL
 
| rowspan="4" |I2C3_SCL
 
| rowspan="4" |CPU.I2C3_SCL
 
| rowspan="4" |CPU.I2C3_SCL
−
| rowspan="4" |G8
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,892: Line 1,896:
 
| rowspan="4" |SAI3_TXFS
 
| rowspan="4" |SAI3_TXFS
 
| rowspan="4" |CPU.SAI3_TXFS
 
| rowspan="4" |CPU.SAI3_TXFS
−
| rowspan="4" |G3
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,911: Line 1,915:
 
| rowspan="3" |SPDIF_RX
 
| rowspan="3" |SPDIF_RX
 
| rowspan="3" |CPU.SPDIF_RX
 
| rowspan="3" |CPU.SPDIF_RX
−
| rowspan="3" |G6
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 1,927: Line 1,931:
 
| rowspan="3" |SPDIF_TX
 
| rowspan="3" |SPDIF_TX
 
| rowspan="3" |CPU.SPDIF_TX
 
| rowspan="3" |CPU.SPDIF_TX
−
| rowspan="3" |F6
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 1,943: Line 1,947:
 
| rowspan="4" |SAI3_MCLK
 
| rowspan="4" |SAI3_MCLK
 
| rowspan="4" |CPU.SAI3_MCLK
 
| rowspan="4" |CPU.SAI3_MCLK
−
| rowspan="4" |D3
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,962: Line 1,966:
 
| rowspan="4" |I2C3_SDA
 
| rowspan="4" |I2C3_SDA
 
| rowspan="4" |CPU.I2C3_SDA
 
| rowspan="4" |CPU.I2C3_SDA
−
| rowspan="4" |E9
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 1,981: Line 1,985:
 
| rowspan="4" |SAI3_TXC
 
| rowspan="4" |SAI3_TXC
 
| rowspan="4" |CPU.SAI3_TXC
 
| rowspan="4" |CPU.SAI3_TXC
−
| rowspan="4" |C4
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 2,000: Line 2,004:
 
| rowspan="4" |SAI3_TXD
 
| rowspan="4" |SAI3_TXD
 
| rowspan="4" |CPU.SAI3_TXD
 
| rowspan="4" |CPU.SAI3_TXD
−
| rowspan="4" |C3
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 2,019: Line 2,023:
 
| rowspan="2" |GPIO1_IO10
 
| rowspan="2" |GPIO1_IO10
 
| rowspan="2" |CPU.GPIO1_IO10
 
| rowspan="2" |CPU.GPIO1_IO10
−
| rowspan="2" |M7
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 2,042: Line 2,046:
 
| rowspan="4" |SAI5_MCLK
 
| rowspan="4" |SAI5_MCLK
 
| rowspan="4" |CPU.SAI5_MCLK
 
| rowspan="4" |CPU.SAI5_MCLK
−
| rowspan="4" |K4
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 2,061: Line 2,065:
 
| rowspan="4" |GPIO1_IO15
 
| rowspan="4" |GPIO1_IO15
 
| rowspan="4" |CPU.GPIO1_IO15
 
| rowspan="4" |CPU.GPIO1_IO15
−
| rowspan="4" |J6
+
| rowspan="4" |
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 2,080: Line 2,084:
 
| rowspan="3" |SAI5_RXFS
 
| rowspan="3" |SAI5_RXFS
 
| rowspan="3" |CPU.SAI5_RXFS
 
| rowspan="3" |CPU.SAI5_RXFS
−
| rowspan="3" |N4
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,096: Line 2,100:
 
| rowspan="3" |SAI5_RXC
 
| rowspan="3" |SAI5_RXC
 
| rowspan="3" |CPU.SAI5_RXC
 
| rowspan="3" |CPU.SAI5_RXC
−
| rowspan="3" |L5
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,112: Line 2,116:
 
| rowspan="3" |SAI2_TXC
 
| rowspan="3" |SAI2_TXC
 
| rowspan="3" |CPU.SAI2_TXC
 
| rowspan="3" |CPU.SAI2_TXC
−
| rowspan="3" |J5
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,128: Line 2,132:
 
| rowspan="3" |SAI2_TXD0
 
| rowspan="3" |SAI2_TXD0
 
| rowspan="3" |CPU.SAI2_TXD0
 
| rowspan="3" |CPU.SAI2_TXD0
−
| rowspan="3" |G5
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,144: Line 2,148:
 
| rowspan="3" |SAI2_TXFS
 
| rowspan="3" |SAI2_TXFS
 
| rowspan="3" |CPU.SAI2_TXFS
 
| rowspan="3" |CPU.SAI2_TXFS
−
| rowspan="3" |H4
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,160: Line 2,164:
 
| rowspan="3" |SAI2_RXD0
 
| rowspan="3" |SAI2_RXD0
 
| rowspan="3" |CPU.SAI2_RXD0
 
| rowspan="3" |CPU.SAI2_RXD0
−
| rowspan="3" |H6
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,176: Line 2,180:
 
| rowspan="3" |SAI5_RXD0
 
| rowspan="3" |SAI5_RXD0
 
| rowspan="3" |CPU.SAI5_RXD0
 
| rowspan="3" |CPU.SAI5_RXD0
−
| rowspan="3" |M5
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,192: Line 2,196:
 
| rowspan="5" |SAI5_RXD1
 
| rowspan="5" |SAI5_RXD1
 
| rowspan="5" |CPU.SAI5_RXD1
 
| rowspan="5" |CPU.SAI5_RXD1
−
| rowspan="5" |L4
+
| rowspan="5" |
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |I/O
 
| rowspan="5" |I/O
Line 2,214: Line 2,218:
 
| rowspan="5" |SAI5_RXD2
 
| rowspan="5" |SAI5_RXD2
 
| rowspan="5" |CPU.SAI5_RXD2
 
| rowspan="5" |CPU.SAI5_RXD2
−
| rowspan="5" |M4
+
| rowspan="5" |
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |I/O
 
| rowspan="5" |I/O
Line 2,236: Line 2,240:
 
| rowspan="5" |SAI5_RXD3
 
| rowspan="5" |SAI5_RXD3
 
| rowspan="5" |CPU.SAI5_RXD3
 
| rowspan="5" |CPU.SAI5_RXD3
−
| rowspan="5" |K5
+
| rowspan="5" |
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |I/O
 
| rowspan="5" |I/O
Line 2,268: Line 2,272:
 
|CLK2_N
 
|CLK2_N
 
|CPU.CLK2_N
 
|CPU.CLK2_N
−
|T22
+
|
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
Line 2,278: Line 2,282:
 
|CLK2_P
 
|CLK2_P
 
|CPU.CLK2_P
 
|CPU.CLK2_P
−
|U22
+
|
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
Line 2,288: Line 2,292:
 
|PCIE1_REF_CLKN
 
|PCIE1_REF_CLKN
 
|CPU.PCIE1_REF_PAD_CLK_N
 
|CPU.PCIE1_REF_PAD_CLK_N
−
|K24
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,298: Line 2,302:
 
|PCIE1_REF_CLKP
 
|PCIE1_REF_CLKP
 
|CPU.PCIE1_REF_PAD_CLK_P
 
|CPU.PCIE1_REF_PAD_CLK_P
−
|K25
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,308: Line 2,312:
 
|PCIE1_RXN
 
|PCIE1_RXN
 
|CPU.PCIE1_RXN_N
 
|CPU.PCIE1_RXN_N
−
|H24
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,318: Line 2,322:
 
|PCIE1_RXP
 
|PCIE1_RXP
 
|CPU.PCIE1_RXN_P
 
|CPU.PCIE1_RXN_P
−
|H25
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,328: Line 2,332:
 
|PCIE1_TXN
 
|PCIE1_TXN
 
|CPU.PCIE1_TXN_N
 
|CPU.PCIE1_TXN_N
−
|J24
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,338: Line 2,342:
 
|PCIE1_TXP
 
|PCIE1_TXP
 
|CPU.PCIE1_TXN_P
 
|CPU.PCIE1_TXN_P
−
|J25
+
|
 
|VDD_PHY_3V3
 
|VDD_PHY_3V3
 
|D
 
|D
Line 2,358: Line 2,362:
 
|CSI1_CLK_N
 
|CSI1_CLK_N
 
|CPU.MIPI_CSI1_CLK_N
 
|CPU.MIPI_CSI1_CLK_N
−
|A22
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,368: Line 2,372:
 
|CSI1_CLK_P
 
|CSI1_CLK_P
 
|CPU.MIPI_CSI1_CLK_P
 
|CPU.MIPI_CSI1_CLK_P
−
|B22
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,378: Line 2,382:
 
|CSI1_D0_N
 
|CSI1_D0_N
 
|CPU.MIPI_CSI1_D0_N
 
|CPU.MIPI_CSI1_D0_N
−
|A23
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,388: Line 2,392:
 
|CSI1_D0_P
 
|CSI1_D0_P
 
|CPU.MIPI_CSI1_D0_P
 
|CPU.MIPI_CSI1_D0_P
−
|B23
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,398: Line 2,402:
 
|CSI1_D1_N
 
|CSI1_D1_N
 
|CPU.MIPI_CSI1_D1_N
 
|CPU.MIPI_CSI1_D1_N
−
|C22
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,408: Line 2,412:
 
|CSI1_D1_P
 
|CSI1_D1_P
 
|CPU.MIPI_CSI1_D1_P
 
|CPU.MIPI_CSI1_D1_P
−
|D22
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,418: Line 2,422:
 
|CSI1_D2_N
 
|CSI1_D2_N
 
|CPU.MIPI_CSI1_D2_N
 
|CPU.MIPI_CSI1_D2_N
−
|B24
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,428: Line 2,432:
 
|CSI1_D2_P
 
|CSI1_D2_P
 
|CPU.MIPI_CSI1_D2_P
 
|CPU.MIPI_CSI1_D2_P
−
|C23
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,438: Line 2,442:
 
|CSI1_D3_N
 
|CSI1_D3_N
 
|CPU.MIPI_CSI1_D3_N
 
|CPU.MIPI_CSI1_D3_N
−
|C21
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,448: Line 2,452:
 
|CSI1_D3_P
 
|CSI1_D3_P
 
|CPU.MIPI_CSI1_D3_P
 
|CPU.MIPI_CSI1_D3_P
−
|D21
+
|
 
| -
 
| -
 
|D
 
|D
Line 2,469: Line 2,473:
 
|NAND_DQS
 
|NAND_DQS
 
|CPU.NAND_DQS
 
|CPU.NAND_DQS
−
|M20
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,480: Line 2,484:
 
| rowspan="3" |NAND_DQS
 
| rowspan="3" |NAND_DQS
 
| rowspan="3" |CPU.NAND_DQS
 
| rowspan="3" |CPU.NAND_DQS
−
| rowspan="3" |M20
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,497: Line 2,501:
 
|NAND_ALE
 
|NAND_ALE
 
|CPU.NAND_ALE
 
|CPU.NAND_ALE
−
|G19
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,508: Line 2,512:
 
| rowspan="3" |NAND_ALE
 
| rowspan="3" |NAND_ALE
 
| rowspan="3" |CPU.NAND_ALE
 
| rowspan="3" |CPU.NAND_ALE
−
| rowspan="3" |G19
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,525: Line 2,529:
 
| rowspan="2" |SD1_CLK
 
| rowspan="2" |SD1_CLK
 
| rowspan="2" |CPU.SD1_CLK
 
| rowspan="2" |CPU.SD1_CLK
−
| rowspan="2" |L25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,540: Line 2,544:
 
| rowspan="3" |NAND_CE0_B
 
| rowspan="3" |NAND_CE0_B
 
| rowspan="3" |CPU.NAND_CE0_B
 
| rowspan="3" |CPU.NAND_CE0_B
−
| rowspan="3" |H19
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,557: Line 2,561:
 
| rowspan="2" |SD1_CMD
 
| rowspan="2" |SD1_CMD
 
| rowspan="2" |CPU.SD1_CMD
 
| rowspan="2" |CPU.SD1_CMD
−
| rowspan="2" |L24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,572: Line 2,576:
 
| rowspan="3" |NAND_CE1_B
 
| rowspan="3" |NAND_CE1_B
 
| rowspan="3" |CPU.NAND_CE1_B
 
| rowspan="3" |CPU.NAND_CE1_B
−
| rowspan="3" |G21
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,589: Line 2,593:
 
| rowspan="2" |SD1_RST_B
 
| rowspan="2" |SD1_RST_B
 
| rowspan="2" |CPU.SD1_RST_B
 
| rowspan="2" |CPU.SD1_RST_B
−
| rowspan="2" |R24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,604: Line 2,608:
 
| rowspan="3" |NAND_CE2_B
 
| rowspan="3" |NAND_CE2_B
 
| rowspan="3" |CPU.NAND_CE2_B
 
| rowspan="3" |CPU.NAND_CE2_B
−
| rowspan="3" |F21
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,621: Line 2,625:
 
| rowspan="2" |SD1_STROBE
 
| rowspan="2" |SD1_STROBE
 
| rowspan="2" |CPU.SD1_STROBE
 
| rowspan="2" |CPU.SD1_STROBE
−
| rowspan="2" |T24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,636: Line 2,640:
 
| rowspan="3" |NAND_CE3_B
 
| rowspan="3" |NAND_CE3_B
 
| rowspan="3" |CPU.NAND_CE3_B
 
| rowspan="3" |CPU.NAND_CE3_B
−
| rowspan="3" |H20
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,653: Line 2,657:
 
|NAND_CLE
 
|NAND_CLE
 
|CPU.NAND_CLE
 
|CPU.NAND_CLE
−
|H21
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,664: Line 2,668:
 
| rowspan="3" |NAND_CLE
 
| rowspan="3" |NAND_CLE
 
| rowspan="3" |CPU.NAND_CLE
 
| rowspan="3" |CPU.NAND_CLE
−
| rowspan="3" |H21
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,681: Line 2,685:
 
| rowspan="2" |SD1_DATA0
 
| rowspan="2" |SD1_DATA0
 
| rowspan="2" |CPU.SD1_DATA0
 
| rowspan="2" |CPU.SD1_DATA0
−
| rowspan="2" |M25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,696: Line 2,700:
 
| rowspan="3" |NAND_DATA00
 
| rowspan="3" |NAND_DATA00
 
| rowspan="3" |CPU.NAND_DATA00
 
| rowspan="3" |CPU.NAND_DATA00
−
| rowspan="3" |G20
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,713: Line 2,717:
 
| rowspan="2" |SD1_DATA1
 
| rowspan="2" |SD1_DATA1
 
| rowspan="2" |CPU.SD1_DATA1
 
| rowspan="2" |CPU.SD1_DATA1
−
| rowspan="2" |M24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,728: Line 2,732:
 
| rowspan="3" |NAND_DATA01
 
| rowspan="3" |NAND_DATA01
 
| rowspan="3" |CPU.NAND_DATA01
 
| rowspan="3" |CPU.NAND_DATA01
−
| rowspan="3" |J20
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,745: Line 2,749:
 
| rowspan="2" |SD1_DATA2
 
| rowspan="2" |SD1_DATA2
 
| rowspan="2" |CPU.SD1_DATA2
 
| rowspan="2" |CPU.SD1_DATA2
−
| rowspan="2" |N25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,760: Line 2,764:
 
| rowspan="3" |NAND_DATA02
 
| rowspan="3" |NAND_DATA02
 
| rowspan="3" |CPU.NAND_DATA02
 
| rowspan="3" |CPU.NAND_DATA02
−
| rowspan="3" |H22
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,777: Line 2,781:
 
| rowspan="2" |SD1_DATA3
 
| rowspan="2" |SD1_DATA3
 
| rowspan="2" |CPU.SD1_DATA3
 
| rowspan="2" |CPU.SD1_DATA3
−
| rowspan="2" |P25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,792: Line 2,796:
 
| rowspan="3" |NAND_DATA03
 
| rowspan="3" |NAND_DATA03
 
| rowspan="3" |CPU.NAND_DATA03
 
| rowspan="3" |CPU.NAND_DATA03
−
| rowspan="3" |J21
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,819: Line 2,823:
 
| rowspan="2" |SD1_DATA4
 
| rowspan="2" |SD1_DATA4
 
| rowspan="2" |CPU.SD1_DATA4
 
| rowspan="2" |CPU.SD1_DATA4
−
| rowspan="2" |N24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,834: Line 2,838:
 
| rowspan="3" |NAND_DATA04
 
| rowspan="3" |NAND_DATA04
 
| rowspan="3" |CPU.NAND_DATA04
 
| rowspan="3" |CPU.NAND_DATA04
−
| rowspan="3" |L20
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,851: Line 2,855:
 
| rowspan="2" |SD1_DATA5
 
| rowspan="2" |SD1_DATA5
 
| rowspan="2" |CPU.SD1_DATA5
 
| rowspan="2" |CPU.SD1_DATA5
−
| rowspan="2" |P24
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,866: Line 2,870:
 
| rowspan="3" |NAND_DATA05
 
| rowspan="3" |NAND_DATA05
 
| rowspan="3" |CPU.NAND_DATA05
 
| rowspan="3" |CPU.NAND_DATA05
−
| rowspan="3" |J22
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,883: Line 2,887:
 
| rowspan="2" |SD1_DATA6
 
| rowspan="2" |SD1_DATA6
 
| rowspan="2" |CPU.SD1_DATA6
 
| rowspan="2" |CPU.SD1_DATA6
−
| rowspan="2" |R25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,898: Line 2,902:
 
| rowspan="3" |NAND_DATA06
 
| rowspan="3" |NAND_DATA06
 
| rowspan="3" |CPU.NAND_DATA06
 
| rowspan="3" |CPU.NAND_DATA06
−
| rowspan="3" |L19
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,915: Line 2,919:
 
| rowspan="2" |SD1_DATA7
 
| rowspan="2" |SD1_DATA7
 
| rowspan="2" |CPU.SD1_DATA7
 
| rowspan="2" |CPU.SD1_DATA7
−
| rowspan="2" |T25
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
 
(NVCC_1V8 on request)
Line 2,930: Line 2,934:
 
| rowspan="3" |NAND_DATA07
 
| rowspan="3" |NAND_DATA07
 
| rowspan="3" |CPU.NAND_DATA07
 
| rowspan="3" |CPU.NAND_DATA07
−
| rowspan="3" |M19
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,947: Line 2,951:
 
|NAND_RE_B
 
|NAND_RE_B
 
|CPU.NAND_RE_B
 
|CPU.NAND_RE_B
−
|K19
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,958: Line 2,962:
 
| rowspan="3" |NAND_RE_B
 
| rowspan="3" |NAND_RE_B
 
| rowspan="3" |CPU.NAND_RE_B
 
| rowspan="3" |CPU.NAND_RE_B
−
| rowspan="3" |K19
+
| rowspan="3" |
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 2,975: Line 2,979:
 
|NAND_READY_B
 
|NAND_READY_B
 
|CPU.NAND_READY_B
 
|CPU.NAND_READY_B
−
|K20
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,986: Line 2,990:
 
| rowspan="2" |NAND_READY_B
 
| rowspan="2" |NAND_READY_B
 
| rowspan="2" |CPU.NAND_READY_B
 
| rowspan="2" |CPU.NAND_READY_B
−
| rowspan="2" |K20
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 3,000: Line 3,004:
 
|NAND_WE_B
 
|NAND_WE_B
 
|CPU.NAND_WE_B
 
|CPU.NAND_WE_B
−
|K22
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 3,011: Line 3,015:
 
| rowspan="2" |NAND_WE_B
 
| rowspan="2" |NAND_WE_B
 
| rowspan="2" |CPU.NAND_WE_B
 
| rowspan="2" |CPU.NAND_WE_B
−
| rowspan="2" |K22
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 3,025: Line 3,029:
 
|NAND_WP_B
 
|NAND_WP_B
 
|CPU.NAND_WP_B
 
|CPU.NAND_WP_B
−
|K21
+
|
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 3,036: Line 3,040:
 
| rowspan="2" |NAND_WP_B
 
| rowspan="2" |NAND_WP_B
 
| rowspan="2" |CPU.NAND_WP_B
 
| rowspan="2" |CPU.NAND_WP_B
−
| rowspan="2" |K21
+
| rowspan="2" |
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 3,057: Line 3,061:
 
|-
 
|-
 
|J1.166
 
|J1.166
−
|CLK1_N
 
−
|CPU.CLK1_N
 
−
|T23
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,067: Line 3,071:
 
|-
 
|-
 
|J1.168
 
|J1.168
−
|CLK1_P
 
−
|CPU.CLK1_P
 
−
|R23
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,077: Line 3,081:
 
|-
 
|-
 
|J1.170
 
|J1.170
−
|USB2_RXN
 
−
|CPU.USB2_RX_N
 
−
|B8
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,087: Line 3,091:
 
|-
 
|-
 
|J1.172
 
|J1.172
−
|USB2_RXP
 
−
|CPU.USB2_RX_P
 
−
|A8
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,097: Line 3,101:
 
|-
 
|-
 
|J1.174
 
|J1.174
−
|USB2_TXN
 
−
|CPU.USB2_TX_N
 
−
|B9
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,107: Line 3,111:
 
|-
 
|-
 
|J1.176
 
|J1.176
−
|USB2_TXP
 
−
|CPU.USB2_TX_P
 
−
|A9
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,117: Line 3,121:
 
|-
 
|-
 
|J1.178
 
|J1.178
−
|USB1_RXN
 
−
|CPU.USB1_RX_N
 
−
|B12
 
 
|
 
|
−
|D
 
 
|
 
|
 
|
 
|
 
|
 
|
−
|-
+
|I/O
 +
|
 +
|
 +
|
 +
|-
 
|J1.180
 
|J1.180
−
|USB1_RXP
 
−
|CPU.USB1_RX_P
 
−
|A12
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,137: Line 3,141:
 
|-
 
|-
 
|J1.182
 
|J1.182
−
|USB1_TXN
 
−
|CPU.USB1_TX_N
 
−
|B13
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,147: Line 3,151:
 
|-
 
|-
 
|J1.184
 
|J1.184
−
|USB1_TXP
 
−
|CPU.USB1_TX_P
 
−
|A13
 
 
|
 
|
−
|D
+
|
 +
|
 +
|
 +
|I/O
 
|
 
|
 
|
 
|
Line 3,159: Line 3,163:
 
|USB1_VBUS
 
|USB1_VBUS
 
|CPU.USB1_VBUS
 
|CPU.USB1_VBUS
−
|D14
+
|F22
−
| -
+
|
 
|S
 
|S
−
|
+
|Connected with 30K resistor
 
|
 
|
 
|
 
|
Line 3,169: Line 3,173:
 
|USB2_VBUS
 
|USB2_VBUS
 
|CPU.USB2_VBUS
 
|CPU.USB2_VBUS
−
|D9
+
|F23
−
| -
+
|
 
|S
 
|S
−
|
+
|Connected with 30K resistor
 
|
 
|
 
|
 
|
Line 3,189: Line 3,193:
 
|USB1_ID
 
|USB1_ID
 
|CPU.USB1_ID
 
|CPU.USB1_ID
−
|C14
+
|D22
−
|VDD_PHY_3V3
+
|VDDA_1V8
 
|I
 
|I
 
|
 
|
Line 3,199: Line 3,203:
 
|USB2_ID
 
|USB2_ID
 
|CPU.USB2_ID
 
|CPU.USB2_ID
−
|C9
+
|D23
−
|VDD_PHY_3V3
+
|VDDA_1V8
 
|I
 
|I
 
|
 
|
Line 3,209: Line 3,213:
 
|USB1_DN
 
|USB1_DN
 
|CPU.USB1_DN
 
|CPU.USB1_DN
−
|B14
+
|A22
 
| -
 
| -
 
|D
 
|D
Line 3,219: Line 3,223:
 
|USB1_DP
 
|USB1_DP
 
|CPU.USB1_DP
 
|CPU.USB1_DP
−
|A14
+
|B22
 
| -
 
| -
 
|D
 
|D
Line 3,229: Line 3,233:
 
|USB2_DP
 
|USB2_DP
 
|CPU.USB2_DP
 
|CPU.USB2_DP
−
|A10
+
|B23
 
| -
 
| -
 
|D
 
|D
Line 3,239: Line 3,243:
 
|USB2_DN
 
|USB2_DN
 
|CPU.USB2_DN
 
|CPU.USB2_DN
−
|B10
+
|A23
 
| -
 
| -
 
|D
 
|D

Revision as of 13:30, 22 January 2021

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History
Version Issue Date Notes
1.0.0 Dec 2020 First release


Connectors and Pinout Table description[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM edge connector 204 pin partially compatible with AXEL Lite SOM TE Connectivity 2-2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:

MITO 8M Mini/Nano TOP view
MITO 8M Mini/Nano BOTTOM view

Below a detailed description of the pinout, grouped in the following tables:

  • two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge

Pinout Table description[edit | edit source]

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the MITO 8M connectors
Internal
connections 		Connections to the components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
  • LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

SODIMM J1 ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 AG14 NVCC_3V3 I/O ALT0 GPIO1_IO00
ALT1 CCM_ENET_PHY_REF_CLK_ROOT
ALT5 CCM_REF_CLK_32K
ALT6 CCM_EXT_CLK1
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 AF14 NVCC_3V3 I/O Internally used for ETH PHY reset, do not connect ALT0 GPIO1_IO01
ALT1 PWM1_OUT
ALT5 CCM_REF_CLK_24M
ALT6 CCM_EXT_CLK2
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK AF8 NVCC_3V3 I/O ALT0 SPDIF1_EXT_CLK
ALT1 PWM1_OUT
ALT5 GPIO5_IO05
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 AD9 NVCC_3V3 I/O ALT0 GPIO1_IO13
ALT1 USB1_OTG_OC
ALT5 PWM2_OUT
J1.45 GPIO1_IO11 CPU.GPIO1_IO11 AC10 NVCC_3V3 I/O Internally used for ETH CLK enable, do not connect ALT0 GPIO1_IO11
ALT1 USB1_OTG_ID
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK E6 NVCC_3V3 I/O ALT0 ECSPI2_SCLK
ALT1 UART4_RX
ALT5 GPIO5_IO10
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI B8 NVCC_3V3 I/O ALT0 ECSPI2_MOSI
ALT1 UART4_TX
ALT5 GPIO5_IO11
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 AG10 NVCC_3V3 I/O ALT0 GPIO1_IO08
ALT1 ENET1_1588_EVENT0_IN
ALT5 USDHC2_RESET_B
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 AF10 NVCC_3V3 I/O ALT0 GPIO1_IO09
ALT1 ENET1_1588_EVENT0_OUT
ALT4 USDHC3_RESET_B
ALT5 SDMA2_EXT_EVENT0
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO A8 NVCC_3V3 I/O ALT0 ECSPI2_MISO
ALT1 UART4_CTS_B
ALT5 GPIO5_IO12
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A6 NVCC_3V3 I/O ALT0 ECSPI2_SS0
ALT1 UART4_RTS_B

(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)

ALT5 GPIO5_IO13
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 AF12 NVCC_3V3 I/O Internally used for MIPI-to-LVDS interrupt, do not connect

Pulled-up to NVCC_3V3

ALT0 GPIO1_IO05
ALT1 M4_NMI
ALT5 CCM_PMIC_READY
J1.63 SAI5_RXD0 CPU.SAI5_RXD0 AD18 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0

( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)

ALT1 SAI1_TX_DATA2
ALT4 PDM_BIT_STREAM0

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4)

ALT5 GPIO3_IO21
J1.65 SAI5_RXD1 CPU.SAI5_RXD1 AC14 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1

(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)

ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC

(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)

ALT3 SAI5_TX_SYNC

(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)

ALT4 PDM_BIT_STREAM1

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)

ALT5 GPIO3_IO22
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 AG11 NVCC_3V3 I/O Internally used for MIPI-to-LVDS enable, do not connect ALT0 GPIO1_IO06
ALT1 ENET1_MDC
ALT5 USDHC1_CD_B
ALT6 CCM_EXT_CLK3
J1.69 SAI2_RXC CPU.SAI2_RXC AB22 NVCC_3V3 I/O ALT0 SAI2_RX_BCLK
ALT1 SAI5_TX_BCLK

(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)

ALT4 UART1_RX
ALT5 GPIO4_IO22
J1.71 SAI2_RXFS CPU.SAI2_RXFS AC19 NVCC_3V3 I/O ALT0 SAI2_RX_SYNC
ALT1 SAI5_TX_SYNC

(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)

ALT2 SAI5_TX_DATA1
ALT3 SAI2_RX_DATA1
ALT4 UART1_TX
ALT5 GPIO4_IO21
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 AB23 NVCC_3V3 I/O ALT0 USDHC2_DATA0
ALT5 GPIO2_IO15
J1.77 SD2_DATA1 CPU.SD2_DATA1 AB24 NVCC_3V3 I/O ALT0 USDHC2_DATA1
ALT5 GPIO2_IO16
J1.79 SD2_DATA2 CPU.SD2_DATA2 V24 NVCC_3V3 I/O ALT0 USDHC2_DATA2
ALT5 GPIO2_IO17
J1.81 SD2_DATA3 CPU.SD2_DATA03 V23 NVCC_3V3 I/O ALT0 USDHC2_DATA3
ALT5 GPIO2_IO18
J1.83 SD2_CMD CPU.SD2_CMD W24 NVCC_3V3 I/O ALT0 USDHC2_CMD
ALT5 GPIO2_IO14
J1.85 SD2_CLK CPU.SD2_CLK W23 NVCC_3V3 I/O ALT0 USDHC2_CLK
ALT5 GPIO2_IO13
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD D18 NVCC_3V3 I/O Internally pulled-up to NVCC_3V3 ALT0 UART3_TX
ALT1 UART1_RTS_B

(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)

ALT2 USDHC3_VSELECT
ALT5 GPIO5_IO27
J1.91 UART3_RXD CPU.UART3_RXD E18 NVCC_3V3 I/O ALT0 UART3_RX
ALT1 UART1_CTS_B
ALT2 USDHC3_RESET_B
ALT5 GPIO5_IO26
J1.93 UART1_TXD CPU.UART1_TXD F13 NVCC_3V3 I/O ALT0 UART1_TX
ALT1 ECSPI3_MOSI
ALT5 GPIO5_IO23
J1.95 UART1_RXD CPU.UART1_RXD E14 NVCC_3V3 I/O ALT0 UART1_RX
ALT1 ECSPI3_SCLK
ALT5 GPIO5_IO22
J1.97 SD2_WP CPU.SD2_WP AA27 NVCC_3V3 I/O ALT0 USDHC2_WP
ALT5 GPIO2_IO20
J1.99 SD2_RST_B CPU.SD2_RESET_B AB26 NVCC_3V3 I/O ALT0 USDHC2_RESET_B
ALT5 GPIO2_IO19
J1.101 I2C2_SCL CPU.I2C2_SCL D10 NVCC_3V3 I/O ALT0 I2C2_SCL
ALT1 ENET1_1588_EVENT1_IN
ALT2 USDHC3_CD_B

(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)

ALT5 GPIO5_IO16
J1.103 I2C2_SDA CPU.I2C2_SDA D9 NVCC_3V3 I/O ALT0 I2C2_SDA
ALT1 ENET1_1588_EVENT1_OUT
ALT2 USDHC3_WP

(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)

ALT5 GPIO5_IO17
J1.105 SAI1_RXD3 CPU.SAI1_RXD3 AF17 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_RX_DATA3
ALT1 SAI5_RX_DATA3

(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)

ALT3 PDM_BIT_STREAM3

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)

ALT4 CORESIGHT_TRACE3
ALT5 GPIO4_IO05
ALT6 SRC_BOOT_CFG3
J1.107 SAI1_TXD3 CPU.SAI1_TXD3 AF21 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_TX_DATA3
ALT1 SAI5_TX_DATA3
ALT4 CORESIGHT_TRACE11
ALT5 GPIO4_IO15
ALT6 SRC_BOOT_CFG11
J1.109 DGND DGND - - G
J1.111 SAI1_TXFS CPU.SAI1_TXFS AB19 NVCC_3V3 I/O ALT0 SAI1_TX_SYNC

(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)

ALT1 SAI5_TX_SYNC

(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)

ALT4 CORESIGHT_EVENTO
ALT5 GPIO4_IO10
J1.113 SAI1_TXC CPU.SAI1_TXC AC18 NVCC_3V3 I/O ALT0 SAI1_TX_BCLK

(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)

ALT1 SAI5_TX_BCLK

(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)

ALT4 CORESIGHT_EVENTI
ALT5 GPIO4_IO11
J1.115 SAI1_TXD0 CPU.SAI1_TXD0 AG20 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_TX_DATA0
ALT1 SAI5_TX_DATA0
ALT4 CORESIGHT_TRACE8
ALT5 GPIO4_IO12
ALT6 SRC_BOOT_CFG8
J1.117 SAI1_TXD1 CPU.SAI1_TXD1 AF20 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_TX_DATA1
ALT1 SAI5_TX_DATA1
ALT4 CORESIGHT_TRACE9
ALT5 GPIO4_IO13
ALT6 SRC_BOOT_CFG9
J1.119 SAI1_TXD2 CPU.SAI1_TXD2 AG21 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_TX_DATA2
ALT1 SAI5_TX_DATA2
ALT4 CORESIGHT_TRACE10
ALT5 GPIO4_IO14
ALT6 SRC_BOOT_CFG10
J1.121 SAI1_RXFS CPU.SAI1_RXFS AG16 NVCC_3V3 I/O ALT0 SAI1_RX_SYNC

(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)

ALT1 SAI5_RX_SYNC

(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)

ALT4 CORESIGHT_TRACE_CLK
ALT5 GPIO4_IO00
J1.123 SAI1_RXC CPU.SAI1_RXC AF16 NVCC_3V3 I/O ALT0 SAI1_RX_BCLK
ALT1 SAI5_RX_BCLK

(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)

ALT4 CORESIGHT_TRACE_CTL
ALT5 GPIO4_IO01
J1.125 SAI1_RXD0 CPU.SAI1_RXD0 AG15 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_RX_DATA0
ALT1 SAI5_RX_DATA0

(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)

ALT2 SAI1_TX_DATA1
ALT3 PDM_BIT_STREAM0

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)

ALT4 CORESIGHT_TRACE0
ALT5 GPIO4_IO02
ALT6 SRC_BOOT_CFG0
J1.127 SAI1_RXD1 CPU.SAI1_RXD1 AF15 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_RX_DATA1
ALT1 SAI5_RX_DATA1

(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)

ALT3 PDM_BIT_STREAM1

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)

ALT4 CORESIGHT_TRACE1
ALT5 GPIO4_IO03
ALT6 SRC_BOOT_CFG1
J1.129 SAI1_RXD2 CPU.SAI1_RXD2 AG17 NVCC_3V3 I/O Internally used for BOOT mode configuration:

can be pulled-up or down depending on

MITO 8M Mini SOM P/N composition

ALT0 SAI1_RX_DATA2
ALT1 SAI5_RX_DATA2

(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)

ALT3 PDM_BIT_STREAM2

(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)

ALT4 CORESIGHT_TRACE2
ALT5 GPIO4_IO04
ALT6 SRC_BOOT_CFG2
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B AA26 NVCC_3V3 I/O ALT0 USDHC2_CD_B
ALT5 GPIO2_IO12
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 B6 NVCC_3V3 I/O ALT0 ECSPI1_SS0
ALT1 UART3_RTS_B

(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)

ALT5 GPIO5_IO09
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D6 NVCC_3V3 I/O ALT0 ECSPI1_SCLK
ALT1 UART3_RX
ALT5 GPIO5_IO06
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO A7 NVCC_3V3 I/O ALT0 ECSPI1_MISO
ALT1 UART3_CTS_B
ALT5 GPIO5_IO08
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 AF13 NVCC_3V3 I/O ALT0 GPIO1_IO03
ALT1 USDHC1_VSELECT
ALT5 SDMA1_EXT_EVENT0
J1.187 UART2_TXD CPU.UART2_TXD E15 NVCC_3V3 I/O used as default Linux console ALT0 UART2_TX
ALT1 ECSPI3_SS0
ALT5 GPIO5_IO25
J1.189 UART2_RXD CPU.UART2_RXD F15 NVCC_3V3 I/O used as default Linux console ALT0 UART2_RXD
ALT1 ECSPI3_MISO
ALT5 GPIO5_IO24
J1.191 UART4_TXD CPU.UART4_TXD F18 NVCC_3V3 I/O ALT0 UART4_TX
ALT1 UART2_RTS_B

(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)

ALT5 GPIO5_IO29
J1.193 UART4_RXD CPU.UART4_RXD F19 NVCC_3V3 I/O ALT0 UART4_RX
ALT1 UART2_CTS_B
ALT2 PCIE1_CLKREQ_B

(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)

ALT5 GPIO5_IO28
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI B7 NVCC_3V3 I/O ALT0 ECSPI1_MOSI
ALT1 UART3_TX
ALT5 GPIO5_IO07
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 AC9 NVCC_3V3 I/O ALT0 GPIO1_IO14
ALT1 USB2_OTG_PWR
ALT4 USDHC3_CD_B

(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)

ALT5 PWM3_OUT
ALT6 CCM_CLKO1
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 AG12 NVCC_3V3 I/O ALT0 GPIO1_IO04
ALT1 USDHC2_VSELECT
ALT5 SDMA1_EXT_EVENT1
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 AB10 NVCC_3V3 I/O ALT0 GPIO1_IO12
ALT1 USB1_OTG_PWR
ALT5 SDMA2_EXT_EVENT1
J1.203 DGND DGND - - G

SODIMM J1 EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 46 - S
J1.16 CPU_ONOFF CPU.ONOFF A25 NVCC_SNVS_1V8 I internal pull-up 100k to NVCC_SNVS_1V8
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESET_MCU

B24

21

NVCC_SNVS_1V8 I/O internal pull-up 100k to NVCC_SNVS_1V8
J1.24 PMIC_PWRON PMIC.PWRON 22 - I internal pull-up 100k to VIN
J1.26 SAI3_RXC CPU.SAI3_RXC AG7 NVCC_3V3 I/O ALT0 SAI3_RX_BCLK
ALT1 GPT1_CLK
ALT2 SAI5_RX_BCLK

(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)

ALT4 UART2_CTS_B
ALT5 GPIO4_IO29
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 NVCC_3V3 I/O Internally used for SW reset, do not connect ALT0 GPIO1_IO02
ALT1 WDOG1_WDOG_B
ALT5 WDOG1_WDOG_ANY
ALT7 SJC_DE_B
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD NVCC_3V3 I/O ALT0 SAI3_RX_DATA0
ALT1 GPT1_COMPARE1
ALT2 SAI5_RX_DATA0
ALT5 GPIO4_IO30
J1.34 SAI2_MCLK CPU.SAI2_MCLK NVCC_3V3 I/O ALT0 SAI2_MCLK
ALT1 SAI5_MCLK
ALT5 GPIO4_IO27
J1.36 SAI3_RXFS CPU.SAI3_RXFS NVCC_3V3 I/O ALT0 SAI3_RX_SYNC
ALT1 GPT1_CAPTURE1
ALT2 SAI5_RX_SYNC
ALT5 GPIO4_IO28
J1.38 I2C3_SCL CPU.I2C3_SCL NVCC_3V3 I/O ALT0 I2C3_SCL
ALT1 PWM4_OUT
ALT2 GPT2_CLK
ALT5 GPIO5_IO18
J1.40 SAI3_TXFS CPU.SAI3_TXFS NVCC_3V3 I/O ALT0 SAI3_TX_SYNC
ALT1 GPT1_CLK
ALT2 SAI5_RX_DATA1
ALT5 GPIO4_IO31
J1.42 SPDIF_RX CPU.SPDIF_RX NVCC_3V3 I/O ALT0 SPDIF1_IN
ALT1 PWM2_OUT
ALT5 GPIO5_IO04
J1.44 SPDIF_TX CPU.SPDIF_TX NVCC_3V3 I/O ALT0 SPDIF1_OUT
ALT1 PWM3_OUT
ALT5 GPIO5_IO03
J1.46 SAI3_MCLK CPU.SAI3_MCLK NVCC_3V3 I/O ALT0 SAI3_MCLK
ALT1 PWM4_OUT
ALT2 SAI5_MCLK
ALT5 GPIO5_IO02
J1.48 I2C3_SDA CPU.I2C3_SDA NVCC_3V3 I/O ALT0 I2C3_SDA
ALT1 PWM3_OUT
ALT2 GPT3_CLK
ALT5 GPIO5_IO19
J1.50 SAI3_TXC CPU.SAI3_TXC NVCC_3V3 I/O ALT0 SAI3_TX_BCLK
ALT1 GPT1_COMPARE2
ALT2 SAI5_RX_DATA2
ALT5 GPIO5_IO00
J1.52 SAI3_TXD CPU.SAI3_TXD NVCC_3V3 I/O ALT0 SAI3_TX_DATA0
ALT1 GPT1_COMPARE3
ALT2 SAI5_RX_DATA3
ALT5 GPIO5_IO01
J1.54 GPIO1_IO10 CPU.GPIO1_IO10 NVCC_3V3 I/O Internally used for ETH PHY interrupt, do not connect ALT0 GPIO1_IO10
ALT1 USB1_OTG_ID
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK NVCC_3V3 I/O ALT0 SAI5_MCLK
ALT1 SAI1_TX_BCLK
ALT2 SAI4_MCLK
ALT5 GPIO3_IO25
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 NVCC_3V3 I/O ALT0 GPIO1_IO15
ALT1 USB2_OTG_OC
ALT5 PWM4_OUT
ALT6 CCM_CLKO2
J1.62 SAI5_RXFS CPU.SAI5_RXFS NVCC_3V3 I/O ALT0 SAI5_RX_SYNC
ALT1 SAI1_TX_DATA0
ALT5 GPIO3_IO19
J1.64 SAI5_RXC CPU.SAI5_RXC NVCC_3V3 I/O ALT0 SAI5_RX_BCLK
ALT1 SAI1_TX_DATA1
ALT5 GPIO3_IO20
J1.66 SAI2_TXC CPU.SAI2_TXC NVCC_3V3 I/O ALT0 SAI2_TX_BCLK
ALT1 SAI5_TX_DATA2
ALT5 GPIO4_IO25
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 NVCC_3V3 I/O ALT0 SAI2_TX_DATA0
ALT1 SAI5_TX_DATA3
ALT5 GPIO4_IO26
J1.70 SAI2_TXFS CPU.SAI2_TXFS NVCC_3V3 I/O ALT0 SAI2_TX_SYNC
ALT1 SAI5_TX_DATA1
ALT5 GPIO4_IO24
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 NVCC_3V3 I/O ALT0 SAI2_RX_DATA0
ALT1 SAI5_TX_DATA0
ALT5 GPIO4_IO23
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0
ALT1 SAI1_TX_DATA2
ALT5 GPIO3_IO21
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1
ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_SYNC
ALT5 GPIO3_IO212
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 NVCC_3V3 I/O ALT0 SAI5_RX_DATA2
ALT1 SAI1_TX_DATA4
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_BCLK
ALT5 GPIO3_IO23
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 NVCC_3V3 I/O ALT0 SAI5_RX_DATA3
ALT1 SAI1_TX_DATA5
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_DATA0
ALT5 GPIO3_IO24
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.86 CLK2_P CPU.CLK2_P VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P - D
J1.122 DGND DGND - - G
J1.124

(NAND on board)

NAND_DQS CPU.NAND_DQS NVCC_3V3 I/O Internally used for NAND, do not connect
J1.124

(eMMC on board)

NAND_DQS CPU.NAND_DQS NVCC_3V3 I/O ALT0 RAWNAND_DQS
ALT1 QSPI_A_DQS
ALT5 GPIO3_IO14
J1.126

(NAND on board)

NAND_ALE CPU.NAND_ALE NVCC_3V3 I/O Internally used for NAND, do not connect
J1.126

(eMMC on board)

NAND_ALE CPU.NAND_ALE NVCC_3V3 I/O ALT0 RAWNAND_ALE
ALT1 QSPI_A_SCLK
ALT5 GPIO3_IO00
J1.128

(NAND on board)

SD1_CLK CPU.SD1_CLK NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CLK
ALT5 GPIO2_IO00
J1.128

(eMMC on board)

NAND_CE0_B CPU.NAND_CE0_B NVCC_3V3 I/O ALT0 RAWNAND_CE0_B
ALT1 QSPI_A_SS0_B
ALT5 GPIO3_IO01
J1.130

(NAND on board)

SD1_CMD CPU.SD1_CMD NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CMD
ALT5 GPIO2_IO01
J1.130

(eMMC on board)

NAND_CE1_B CPU.NAND_CE1_B NVCC_3V3 I/O ALT0 RAWNAND_CE1_B
ALT1 QSPI_A_SS1_B
ALT5 GPIO3_IO02
J1.132

(NAND on board)

SD1_RST_B CPU.SD1_RST_B NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_RESET_B
ALT5 GPIO2_IO10
J1.132

(eMMC on board)

NAND_CE2_B CPU.NAND_CE2_B NVCC_3V3 I/O ALT0 RAWNAND_CE2_B
ALT1 QSPI_B_SS0_B
ALT5 GPIO3_IO03
J1.134

(NAND on board)

SD1_STROBE CPU.SD1_STROBE NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_STROBE
ALT5 GPIO2_IO11
J1.134

(eMMC on board)

NAND_CE3_B CPU.NAND_CE3_B NVCC_3V3 I/O ALT0 RAWNAND_CE3_B
ALT1 QSPI_B_SS1_B
ALT5 GPIO3_IO034
J1.136

(NAND on board)

NAND_CLE CPU.NAND_CLE NVCC_3V3 I/O Internally used for NAND, do not connect
J1.136

(eMMC on board)

NAND_CLE CPU.NAND_CLE NVCC_3V3 I/O ALT0 RAWNAND_CLE
ALT1 QSPI_B_SCLK
ALT5 GPIO3_IO05
J1.138

(NAND on board)

SD1_DATA0 CPU.SD1_DATA0 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA0
ALT5 GPIO2_IO02
J1.138

(eMMC on board)

NAND_DATA00 CPU.NAND_DATA00 NVCC_3V3 I/O ALT0 RAWNAND_DATA00
ALT1 QSPI_A_DATA0
ALT5 GPIO3_IO06
J1.140

(NAND on board)

SD1_DATA1 CPU.SD1_DATA1 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA1
ALT5 GPIO2_IO0
J1.140

(eMMC on board)

NAND_DATA01 CPU.NAND_DATA01 NVCC_3V3 I/O ALT0 RAWNAND_DATA01
ALT1 QSPI_A_DATA1
ALT5 GPIO3_IO07
J1.142

(NAND on board)

SD1_DATA2 CPU.SD1_DATA2 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA2
ALT5 GPIO2_IO04
J1.142

(eMMC on board)

NAND_DATA02 CPU.NAND_DATA02 NVCC_3V3 I/O ALT0 RAWNAND_DATA02
ALT1 QSPI_A_DATA2
ALT5 GPIO3_IO08
J1.144

(NAND on board)

SD1_DATA3 CPU.SD1_DATA3 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA3
ALT5 GPIO2_IO05
J1.144

(eMMC on board)

NAND_DATA03 CPU.NAND_DATA03 NVCC_3V3 I/O ALT0 RAWNAND_DATA03
ALT1 QSPI_A_DATA3
ALT5 GPIO3_IO09
J1.146 DGND DGND - - G
J1.148

(NAND on board)

SD1_DATA4 CPU.SD1_DATA4 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA4
ALT5 GPIO2_IO06
J1.148

(eMMC on board)

NAND_DATA04 CPU.NAND_DATA04 NVCC_3V3 I/O ALT0 RAWNAND_DATA04
ALT1 QSPI_B_DATA0
ALT5 GPIO3_IO10
J1.150

(NAND on board)

SD1_DATA5 CPU.SD1_DATA5 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA5
ALT5 GPIO2_IO07
J1.150

(eMMC on board)

NAND_DATA05 CPU.NAND_DATA05 NVCC_3V3 I/O ALT0 RAWNAND_DATA05
ALT1 QSPI_B_DATA1
ALT5 GPIO3_IO11
J1.152

(NAND on board)

SD1_DATA6 CPU.SD1_DATA6 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA6
ALT5 GPIO2_IO08
J1.152

(eMMC on board)

NAND_DATA06 CPU.NAND_DATA06 NVCC_3V3 I/O ALT0 RAWNAND_DATA06
ALT1 QSPI_B_DATA2
ALT5 GPIO3_IO12
J1.154

(NAND on board)

SD1_DATA7 CPU.SD1_DATA7 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA7
ALT5 GPIO2_IO09
J1.154

(eMMC on board)

NAND_DATA07 CPU.NAND_DATA07 NVCC_3V3 I/O ALT0 RAWNAND_DATA07
ALT1 QSPI_B_DATA3
ALT5 GPIO3_IO13
J1.156

(NAND on board)

NAND_RE_B CPU.NAND_RE_B NVCC_3V3 I/O Internally used for NAND, do not connect
J1.156

(eMMC on board)

NAND_RE_B CPU.NAND_RE_B NVCC_3V3 I/O ALT0 RAWNAND_RE_B
ALT1 QSPI_B_DQS
ALT5 GPIO3_IO15
J1.158

(NAND on board)

NAND_READY_B CPU.NAND_READY_B NVCC_3V3 I/O Internally used for NAND, do not connect
J1.158

(eMMC on board)

NAND_READY_B CPU.NAND_READY_B NVCC_3V3 I/O ALT0 RAWNAND_READY_B
ALT5 GPIO3_IO16
J1.160

(NAND on board)

NAND_WE_B CPU.NAND_WE_B NVCC_3V3 I/O Internally used for NAND, do not connect
J1.160

(eMMC on board)

NAND_WE_B CPU.NAND_WE_B NVCC_3V3 I/O ALT0 RAWNAND_WE_B
ALT5 GPIO3_IO17
J1.162

(NAND on board)

NAND_WP_B CPU.NAND_WP_B NVCC_3V3 I/O Internally used for NAND, do not connect
J1.162

(eMMC on board)

NAND_WP_B CPU.NAND_WP_B NVCC_3V3 I/O ALT0 RAWNAND_WP_B
ALT5 GPIO3_IO18
J1.164 DGND DGND - - G
J1.166 I/O
J1.168 I/O
J1.170 I/O
J1.172 I/O
J1.174 I/O
J1.176 I/O
J1.178 I/O
J1.180 I/O
J1.182 I/O
J1.184 I/O
J1.186 USB1_VBUS CPU.USB1_VBUS F22 S Connected with 30K resistor
J1.188 USB2_VBUS CPU.USB2_VBUS F23 S Connected with 30K resistor
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID D22 VDDA_1V8 I
J1.194 USB2_ID CPU.USB2_ID D23 VDDA_1V8 I
J1.196 USB1_DN CPU.USB1_DN A22 - D
J1.198 USB1_DP CPU.USB1_DP B22 - D
J1.200 USB2_DP CPU.USB2_DP B23 - D
J1.202 USB2_DN CPU.USB2_DN A23 - D
J1.204 DGND DGND - - G
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