Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/General Information/Processor and memory subsystem"
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|- | |- | ||
|GPU | |GPU | ||
| − | | colspan="2" | | + | | colspan="2" |3D: Vivante GC NanoUltra (1 Shader)<br>2D: Vivante GC320 |
OpenGL ES 1.1, 2.0, 3.0, 3.1 | OpenGL ES 1.1, 2.0, 3.0, 3.1 | ||
Open CL 1.2 | Open CL 1.2 | ||
| Line 62: | Line 62: | ||
|- | |- | ||
|VPU | |VPU | ||
| − | | colspan="2" | | + | | colspan="2" |1080p60 HEVC/H.264, VP8, VP9, H.265 decoder |
| − | |||
| − | + | 1080p60 H.264, VP8 encoder | |
| − | |||
| − | |||
|- | |- | ||
|Display | |Display | ||
Controller | Controller | ||
| − | | colspan="2" |Dual Independent | + | | colspan="2" |Dual Independent LVDS channel |
Display Support | Display Support | ||
| − | up | + | up to 1080p60 |
|- | |- | ||
|Video | |Video | ||
Output | Output | ||
| − | | colspan="2" | | + | | colspan="2" |1x MIPI-DSI (with MIPI to LVDS bridge) |
| − | 1x MIPI-DSI | ||
| − | (with MIPI to LVDS bridge) | ||
|- | |- | ||
|Camera | |Camera | ||
Input | Input | ||
| − | | colspan="2" | | + | | colspan="2" |1x MIPI CSI (4-lanes) |
| − | (4-lanes | ||
|- | |- | ||
|PCIe | |PCIe | ||
| − | | colspan="2" | | + | | colspan="2" |1x PCIe 2.1 (1-lane) |
| − | (1-lane | ||
|- | |- | ||
|USB | |USB | ||
| − | | colspan="2" |2x USB | + | | colspan="2" |2x USB 2.0 OTG |
| − | |||
|- | |- | ||
| − | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison | + | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Mini models comparison |
|} | |} | ||
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=== NAND flash bank === | === NAND flash bank === | ||
| + | {| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;" | ||
| + | | [[File:TBD.png|30px]] | ||
| + | | '''Section not completed yet''' | ||
| + | |} | ||
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications: | Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications: | ||
| Line 153: | Line 149: | ||
=== Memory map === | === Memory map === | ||
| − | For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/webapp/Download?colCode= | + | For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/webapp/Download?colCode=IMX8MMRM i.MX8M Mini Applications Processor Reference Manual] |
=== Power supply unit === | === Power supply unit === | ||
Revision as of 13:40, 23 February 2021
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TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)
Contents
Processor and memory subsystem[edit | edit source]
The heart of MITO 8M Mini/Nano module is composed by the following components:
- i.MX8M Mini SoC application processor
- Power supply unit
- LPDDR4 memory bank
- eMMC or NAND flash banks
- Connectors:
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
- partially compatible with AXEL Lite SOM
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main MITO 8M Mini/Nano components.
Processor Info[edit | edit source]
| Processor | i.MX8M Mini Dual | i.MX8M Mini Quad |
| # Cores | 2x Arm® Cortex®-A53
1x Arm® Cortex®-M4 |
4x Arm® Cortex®-A53
1x Arm® Cortex®-M4 |
| Clock | 1.3 GHz
1.6 GHz | |
| L2
Cache |
1 MB | |
| LPDDR4 | 32 bit @ 1600 MHz
(LPDDR4-3200) | |
| GPU | 3D: Vivante GC NanoUltra (1 Shader) 2D: Vivante GC320 OpenGL ES 1.1, 2.0, 3.0, 3.1 Open CL 1.2 Vulkan | |
| VPU | 1080p60 HEVC/H.264, VP8, VP9, H.265 decoder
1080p60 H.264, VP8 encoder | |
| Display
Controller |
Dual Independent LVDS channel
Display Support up to 1080p60 | |
| Video
Output |
1x MIPI-DSI (with MIPI to LVDS bridge) | |
| Camera
Input |
1x MIPI CSI (4-lanes) | |
| PCIe | 1x PCIe 2.1 (1-lane) | |
| USB | 2x USB 2.0 OTG | |
RAM memory bank[edit | edit source]
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
| CPU connection | Multi-mode DDR controller (MMDC) |
| Size max | 4 GB |
| Width | 32 bit |
| Speed | 1600 MHz |
eMMC flash bank[edit | edit source]
On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
| CPU connection | SDIO1 |
| Size min | 4 GB |
| Size max | 64 GB |
| Bootable | Yes |
NAND flash bank[edit | edit source]
|
Section not completed yet |
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
| CPU connection | Raw NAND flash controller |
| Page size | TBD |
| Size min | TBD |
| Size max | TBD |
| Width | 8 bit |
| Chip select | TBD |
| Bootable | Yes |
Memory map[edit | edit source]
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX8M Mini Applications Processor Reference Manual
Power supply unit[edit | edit source]
MITO 8M Mini embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
