Difference between revisions of "ETRA SOM/ETRA Hardware/Power and Reset/System boot"

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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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__FORCETOC__
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<section begin="Body" />
  
 
== System boot ==
 
== System boot ==
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* determines whether the boot is secure or non-secure
 
* determines whether the boot is secure or non-secure
 
* performs some initialization of the system and clean-ups
 
* performs some initialization of the system and clean-ups
 +
* reads the OTP settings
 
* reads the mode pins to determine the primary boot device
 
* reads the mode pins to determine the primary boot device
 
* once it is satisfied, it executes the boot code
 
* once it is satisfied, it executes the boot code
  
 +
=== Boot options ===
  
 +
The default primary boot device is internally set by pull-up or pull-down resistors according to the Boot Mode fileld of the ordering code.
  
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''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
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The BOOT_MODEx signals are also present on the SoM connector to override the primary boot device.
  
 +
The following table shows all the available options:
  
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== Boot options ==
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{| class="wikitable" style="width:50%;"
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|-
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Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
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|'''BOOT_MODE2'''
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* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)
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|'''BOOT_MODE1'''
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* 1: NAND / SD option (SOM code: DXLxxxx1xxR)
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|'''BOOT_MODE0'''
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For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
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|'''PRIMARY BOOT DEVICE'''
 +
|-
 +
|0
 +
|0
 +
|0
 +
|UART and USB
 +
|-
 +
|0
 +
|0
 +
|1
 +
|Serial NOR on QUADSPI
 +
|-
 +
|0
 +
|1
 +
|0
 +
|eMMC on SDMMC2
 +
|-
 +
|0
 +
|1
 +
|1
 +
|SLC NAND on FMC
 +
|-
 +
|1
 +
|0
 +
|0
 +
|no boot (for debug access)
 +
|-
 +
|1
 +
|0
 +
|1
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|SD card on SDMMC1
 +
|-
 +
|1
 +
|1
 +
|0
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|UART and USB
 +
|-
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|1
 +
|1
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|1
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|Serial NAND on QUADSPI
 +
|}
  
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In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
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Use 1k resistors either to VDD or DGND to drive externally the BOOT_MODEx signals.
  
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=== SPI NOR / SD option ===
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=== On board OTP ===
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Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
−
* BOOT_MODE_SEL = 0
 
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** primary boot device is SD1
 
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* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
 
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* BOOT_MODE_SEL = 1 or floating
 
−
** primary boot device is SPI NOR flash connected to eCSPI1
 
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** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
 
  
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=== NAND / SD option ===
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The reading of BOOT_MODEx pins can be disabled by OTP configuration, in this case the OTP settings are used by the ROM code to determine the boot device.
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Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
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* BOOT_MODE_SEL = 0
 
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** primary boot device is SD1
 
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** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
 
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* BOOT_MODE_SEL = 1 or floating
 
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** primary boot device is NAND flash
 
−
** in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
 
  
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===Important note for DualLite/Solo based products (''manufacture mode'' management)===
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Boot sources can be individually disabled by the OTP settings.
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When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
 
  
 
----
 
----
  
 
[[Category:ETRA]]
 
[[Category:ETRA]]

Latest revision as of 11:40, 8 January 2024

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History
Issue Date Notes
2021/02/24 First Release




System boot[edit | edit source]

The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:

  • determines whether the boot is secure or non-secure
  • performs some initialization of the system and clean-ups
  • reads the OTP settings
  • reads the mode pins to determine the primary boot device
  • once it is satisfied, it executes the boot code

Boot options[edit | edit source]

The default primary boot device is internally set by pull-up or pull-down resistors according to the Boot Mode fileld of the ordering code.

The BOOT_MODEx signals are also present on the SoM connector to override the primary boot device.

The following table shows all the available options:

BOOT_MODE2 BOOT_MODE1 BOOT_MODE0 PRIMARY BOOT DEVICE
0 0 0 UART and USB
0 0 1 Serial NOR on QUADSPI
0 1 0 eMMC on SDMMC2
0 1 1 SLC NAND on FMC
1 0 0 no boot (for debug access)
1 0 1 SD card on SDMMC1
1 1 0 UART and USB
1 1 1 Serial NAND on QUADSPI

Use 1k resistors either to VDD or DGND to drive externally the BOOT_MODEx signals.

On board OTP[edit | edit source]

The reading of BOOT_MODEx pins can be disabled by OTP configuration, in this case the OTP settings are used by the ROM code to determine the boot device.

Boot sources can be individually disabled by the OTP settings.

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