a000298_approval, dave_user
551
edits
Changes
WIP
<section begin="History" />
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
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|}
<section end="History" /><section begin="Body" />
== Reset scheme and control signals ==
[[File:ETRA-reset-scheme.png | 800px]]
''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:''
* MRST
* SYSRST
* ...
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''
=== VDD ===
Some signals that are related to reset circuitry are pulled-up to VDD rail. This voltage is generated by the PMIC and act as power good to switch on/off the all the peripheral that could back power the CPU.
=== NRST ===
Rest signal, tie to DGND to reset the system. It is driven by the PMIC to set the CPU in reset state.
=== SOM_PGOOD ===
This is a convencional signal to drive DC/DC enable inputs or switch on/off control signals. It is connected to the VDD through a 22Ohm resistor.
=== PONKEYn ===
User power on key (active low with internal pull-up), used to wake up the sysytem from power down.
=== NRST_CORE ===
Reset signal for the core, to be used if the VDD_CORE is not disabled during the reset. Internally tied to NRST signal.
=== PWR_ON ===
=== PDR_ON ===
=== PDR_ON_CORE ===
=== PWR_LP ===
=== PMIC_VSNVS ===