Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/USART"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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==Peripheral USART == | ==Peripheral USART == | ||
| − | USART provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format. | + | UART (USART on STM32MP1) provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format. |
=== Description === | === Description === | ||
| − | The USART interface available on ETRA | + | The USART interface available on ETRA SOM is based on STM32MP1 SoC. |
The USART port supports the following standards and features: | The USART port supports the following standards and features: | ||
Latest revision as of 11:43, 8 January 2024
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Peripheral USART[edit | edit source]
UART (USART on STM32MP1) provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format.
Description[edit | edit source]
The USART interface available on ETRA SOM is based on STM32MP1 SoC.
The USART port supports the following standards and features:
- full-duplex asynchronous communication
- baud rate generator systems
- two internal FIFOs for transmit and receive data
- auto baud rate detection
- programmable data word length (7, 8 or 9 bits)
- programmable data order with MSB-first or LSB-first shifting
- configurable stop bits (1 or 2 stop bits)
- synchronous master/slave mode and clock output/input for synchronous communications
- single-wire Half-duplex communications
- continuous communications using DMA
- swappable Tx/Rx pin configuration
- hardware flow control for modem and RS-485 transceiver
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
