Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/QUADSPI"

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__FORCETOC__
 
__FORCETOC__
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<section begin="Body" />
  
 
==Peripheral QUADSPI ==
 
==Peripheral QUADSPI ==
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The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories.
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
 
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''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
 
  
 
=== Description  ===
 
=== Description  ===
  
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The QUADSPI interface available on ETRA is based on xxxxx ''TBD:SOC name'' SoC.  
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The QUADSPI interface available on ETRA SoM is based on STM32MP1 SoC.  
  
 
The QUADSPI port supports the following standards and features:
 
The QUADSPI port supports the following standards and features:
  
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* High-Definition Multimedia Interface Specification, Version 1.4a
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* three functional modes: indirect, status-polling, and memory-mapped
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* Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions.
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** indirect mode: all the operations are performed using the QUADSPI registers
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* Support for 4k x 2k and 3D video formats
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**status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting
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* Support for up to 16-bit Deep Color modes
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**memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory
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*dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel
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*integrated FIFO for reception and transmission
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*8, 16, and 32-bit data accesses
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*DMA channel for indirect mode operations
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*interrupt generation on FIFO threshold, timeout, operation complete, and access error
  
 
===Pin mapping===
 
===Pin mapping===

Revision as of 16:07, 30 December 2020

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History
Version Issue Date Notes
0.9.0 Dec 2020 First Draft
[TBD_link X.Y.Z] Month Year TBD
... ... ...



Peripheral QUADSPI[edit | edit source]

The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories.

Description[edit | edit source]

The QUADSPI interface available on ETRA SoM is based on STM32MP1 SoC.

The QUADSPI port supports the following standards and features:

  • three functional modes: indirect, status-polling, and memory-mapped
    • indirect mode: all the operations are performed using the QUADSPI registers
    • status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting
    • memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory
  • dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel
  • integrated FIFO for reception and transmission
  • 8, 16, and 32-bit data accesses
  • DMA channel for indirect mode operations
  • interrupt generation on FIFO threshold, timeout, operation complete, and access error

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section

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