Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/GPIOs"

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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
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* external interrupt capability (unavailable in analog mode)  
 
* external interrupt capability (unavailable in analog mode)  
 
A secondary GPIOs interface available on ETRA SoM is based on ADP5589 I/O expander. This expander is controlled by an internal I2C BUS.
 
A secondary GPIOs interface available on ETRA SoM is based on ADP5589 I/O expander. This expander is controlled by an internal I2C BUS.
 
==== Additional GPIO interface ====
 
ETRA SOM has an optional device, ADP5589 GPIO port, which supports the following standards and features:
 
 
* output states: push-pull or open drain + pull-up/down
 
* input states: floating, pull-up/down, IRQ
 
* keypad decoding for matrix up to 11 × 8
 
* key press/release interrupts
 
* dual programmable logic blocks
 
* PWM generator
 
* clock divider
 
* reset generators
 
 
Please refer to the ETRA SOM [[ETRA_SOM/Part_number_composition | part number composition]] for the related order code option.
 
  
 
===Pin mapping===
 
===Pin mapping===

Latest revision as of 11:44, 8 January 2024

History
Issue Date Notes
2020/12/31 First Release



Peripheral GPIOs[edit | edit source]

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.

Description[edit | edit source]

The primary GPIOs interface available on ETRA SOM is based on STM32MP1 SoC.

The STM32MP1 GPIO ports supports the following standards and features:

  • output states: push-pull or open drain + pull-up/down
  • speed selection for each I/O
  • input states: floating, pull-up/down, analog
  • bit set and reset register for atomic read/modify access
  • analog function
  • fast toggle capable of changing every two clock cycles
  • external interrupt capability (unavailable in analog mode)

A secondary GPIOs interface available on ETRA SoM is based on ADP5589 I/O expander. This expander is controlled by an internal I2C BUS.

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section