Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/Ethernet"
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__FORCETOC__ | __FORCETOC__ | ||
| − | <section begin=Body/> | + | <section begin="Body" /> |
==Peripheral Ethernet == | ==Peripheral Ethernet == | ||
| + | The Ethernet peripheral enables the devices to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. | ||
| − | + | === Description === | |
| − | + | The 10/100/1000-Mbit/s Ethernet interface available on ETRA SoM is based on STM32MP1 SoC. | |
| − | + | The SoC is directly interfaced with an ETH PHY chip (MICROCHIP KSZ8091RNAIA) that has the following features: | |
| + | * Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full) | ||
| + | * On-Chip Termination Resistors for the Differential Pairs | ||
| + | * HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections | ||
| + | * Energy Efficient Ethernet (EEE) support with Low-Power Idle (LPI) mode for 100BASE-TX and Transmit Amplitude Reduction with 10BASE-TE option | ||
| + | |||
| + | * Wake-on-LAN (WoL) Support with Either Magic Packet, Link Status Change, or Robust Custom-Packet Detection | ||
| − | The Ethernet | + | === Important note for the external magnetic connection === |
| + | The Ethernet peripheral requires an external insulator magnetic on the carrier board. | ||
| − | The | + | The two transformer center tap pins on the PHY side should not be connected to any power supply source on the board; rather, the center tap pins should be separated from one another and connected through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode voltage could be different between the four differential pairs, depending on the connected speed mode. |
| − | + | See section 11 (Magnetic connection and selection) on KSZ8091RN datasheet for more details. | |
| − | |||
| − | |||
| − | |||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 09:36, 30 December 2020
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Contents
Peripheral Ethernet[edit | edit source]
The Ethernet peripheral enables the devices to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard.
Description[edit | edit source]
The 10/100/1000-Mbit/s Ethernet interface available on ETRA SoM is based on STM32MP1 SoC.
The SoC is directly interfaced with an ETH PHY chip (MICROCHIP KSZ8091RNAIA) that has the following features:
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- On-Chip Termination Resistors for the Differential Pairs
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections
- Energy Efficient Ethernet (EEE) support with Low-Power Idle (LPI) mode for 100BASE-TX and Transmit Amplitude Reduction with 10BASE-TE option
- Wake-on-LAN (WoL) Support with Either Magic Packet, Link Status Change, or Robust Custom-Packet Detection
Important note for the external magnetic connection[edit | edit source]
The Ethernet peripheral requires an external insulator magnetic on the carrier board.
The two transformer center tap pins on the PHY side should not be connected to any power supply source on the board; rather, the center tap pins should be separated from one another and connected through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode voltage could be different between the four differential pairs, depending on the connected speed mode.
See section 11 (Magnetic connection and selection) on KSZ8091RN datasheet for more details.
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
