Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/DAC"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ||
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=== Description === | === Description === | ||
| − | The DAC interface available on ETRA | + | The DAC interface available on ETRA SOM is based on STM32MP1 SoC. |
The DAC port supports the following standards and features: | The DAC port supports the following standards and features: | ||
| − | * | + | * one DAC interface, maximum two output channels |
| − | * | + | * synchronized update capability |
| − | * | + | * noise-wave and Triangular-wave generation |
| − | * | + | * dual DAC channel for independent or simultaneous conversions |
* DMA capability for each channel | * DMA capability for each channel | ||
| − | * | + | * external triggers for conversion |
* DAC output channel buffered/unbuffered modes | * DAC output channel buffered/unbuffered modes | ||
Latest revision as of 11:44, 8 January 2024
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| 2020/12/31 | First Release | ||
Peripheral DAC[edit | edit source]
Description[edit | edit source]
The DAC interface available on ETRA SOM is based on STM32MP1 SoC.
The DAC port supports the following standards and features:
- one DAC interface, maximum two output channels
- synchronized update capability
- noise-wave and Triangular-wave generation
- dual DAC channel for independent or simultaneous conversions
- DMA capability for each channel
- external triggers for conversion
- DAC output channel buffered/unbuffered modes
Pin mapping[edit | edit source]
DAC I/O connections:
- DAC1_OUT1 on PA4
- DAC1_OUT2 on PA5
The Pin mapping is described in the Pinout table section
