Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/CAN"

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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
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=== Description  ===
 
=== Description  ===
  
The CAN interface available on ETRA SoM is based on STM32MP1 SoC.  
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The CAN interface available on ETRA SOM is based on STM32MP1 SoC.  
  
 
The CAN port supports the following standards and features:
 
The CAN port supports the following standards and features:
  
* two Flexble Data CAN (FDCAN) modules with shared message RAM and  a clock calibration unit  
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* two Flexible Data CAN (FDCAN) modules with shared message RAM and  a clock calibration unit  
 
*compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0
 
*compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0
 
*the first CAN module supports time triggered CAN (TTCAN), specified in ISO 11898-4
 
*the first CAN module supports time triggered CAN (TTCAN), specified in ISO 11898-4

Latest revision as of 11:41, 8 January 2024

History
Issue Date Notes
2020/12/31 First Release



Peripheral CAN[edit | edit source]

The Controller Area Network (CAN) is a robust standard BUS used in automotive applications. It allows multiple devices to transmit at the same time, the highest priority device continues the transmission while the others wait for the next available slot.

An external CAN tranciever is needed to operate.

Description[edit | edit source]

The CAN interface available on ETRA SOM is based on STM32MP1 SoC.

The CAN port supports the following standards and features:

  • two Flexible Data CAN (FDCAN) modules with shared message RAM and a clock calibration unit
  • compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0
  • the first CAN module supports time triggered CAN (TTCAN), specified in ISO 11898-4
  • 10 Kbyte message RAM implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TTCAN)

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section