ETRA SOM/ETRA Hardware/Peripherals/ADC

History
Version	Issue Date	Notes
0.9.0	Dec 2020	First Draft
[TBD_link X.Y.Z]	Month Year	TBD
...	...	...

Contents

Peripheral ADCEdit

DescriptionEdit

The ADC interface available on ETRA SoM is based on STM32MP1 SoC.

The ADC port supports the following standards and features:

• up to 2x ADCs which can operate in dual mode
• 16, 14, 12, 10 or 8-bit configurable resolution
• ADC conversion time is independent from the AHB bus clock frequency
• can manage Single-ended or differential inputs
• self-calibration (both offset and linearity)
• up to 6 fast channels
• up to 14 slow channels
• speed adaptive low-power mode to reduce ADC consumption when operating at low frequency
• 3 analog watchdogs per ADC
• ADC input range from DGND to VDD

Pin mappingEdit

Each CPU port can be configured as analog input.

The Pin mapping is described in the Pinout table section

---