Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/ADC"
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Revision as of 13:26, 31 December 2020
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| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 1.0.0 | Dec 2020 | First Release | |
Peripheral ADC[edit | edit source]
Description[edit | edit source]
The ADC interface available on ETRA SoM is based on STM32MP1 SoC.
The ADC port supports the following standards and features:
- up to 2x ADCs which can operate in dual mode
- 16, 14, 12, 10 or 8-bit configurable resolution
- ADC conversion time is independent from the AHB bus clock frequency
- can manage Single-ended or differential inputs
- self-calibration (both offset and linearity)
- up to 6 fast channels
- up to 14 slow channels
- speed adaptive low-power mode to reduce ADC consumption when operating at low frequency
- 3 analog watchdogs per ADC
- ADC input range from DGND to VDD
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
