Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/ADC"
< ETRA SOM | ETRA Hardware
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| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date |
| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First Draft |
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| − | <section end=History/> | + | <section end="History" /> |
__FORCETOC__ | __FORCETOC__ | ||
| − | <section begin=Body/> | + | <section begin="Body" /> |
==Peripheral ADC == | ==Peripheral ADC == | ||
| − | |||
| − | |||
| − | |||
=== Description === | === Description === | ||
| − | The ADC interface available on ETRA is based on | + | The ADC interface available on ETRA SoM is based on STM32MP1 SoC. |
The ADC port supports the following standards and features: | The ADC port supports the following standards and features: | ||
| − | * | + | * up to 2x ADCs which can operate in dual mode |
| − | * | + | * 16, 14, 12, 10 or 8-bit configurable resolution |
| − | * | + | * ADC conversion time is independent from the AHB bus clock frequency |
| − | * | + | * can manage Single-ended or differential inputs |
| + | * self-calibration (both offset and linearity) | ||
| + | * up to 6 fast channels | ||
| + | * up to 14 slow channels | ||
| + | *speed adaptive low-power mode to reduce ADC consumption when operating at low frequency | ||
| + | *3 analog watchdogs per ADC | ||
| + | *ADC input range from DGND to VDD | ||
===Pin mapping=== | ===Pin mapping=== | ||
| + | Each CPU port can be configured as analog input. | ||
The Pin mapping is described in the [[ETRA SOM/ETRA Hardware/Pinout_Table | Pinout table section]] | The Pin mapping is described in the [[ETRA SOM/ETRA Hardware/Pinout_Table | Pinout table section]] | ||
Revision as of 16:20, 30 December 2020
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| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 0.9.0 | Dec 2020 | First Draft | |
| [TBD_link X.Y.Z] | Month Year | TBD | |
| ... | ... | ... | |
Peripheral ADC[edit | edit source]
Description[edit | edit source]
The ADC interface available on ETRA SoM is based on STM32MP1 SoC.
The ADC port supports the following standards and features:
- up to 2x ADCs which can operate in dual mode
- 16, 14, 12, 10 or 8-bit configurable resolution
- ADC conversion time is independent from the AHB bus clock frequency
- can manage Single-ended or differential inputs
- self-calibration (both offset and linearity)
- up to 6 fast channels
- up to 14 slow channels
- speed adaptive low-power mode to reduce ADC consumption when operating at low frequency
- 3 analog watchdogs per ADC
- ADC input range from DGND to VDD
Pin mapping[edit | edit source]
Each CPU port can be configured as analog input.
The Pin mapping is described in the Pinout table section
