ETRA SOM/ETRA Hardware/General Information/Processor and memory subsystem

History
Version	Issue Date	Notes
0.9.0	12/2020	First Draft
[TBD_link X.Y.Z]	Month Year	TBD
...	...	...

TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)

Contents

Processor and memory subsystemEdit

The heart of ETRA module is composed by the following components:

• STM32MP1 SoC application processor
• Power supply unit
• DDR3L memory banks
• NOR and NAND flash banks
• SODIMM-DDR3 form-factor and connector with interfaces signals

This chapter shortly describes the main ETRA components.

Processor InfoEdit

Table: STM32MP1 models comparison

Processor	# Cores	Clock	L2 Cache	DDR3	MCU	Graphics Acceleration	Temp grade
STM32MP151DAB3	1	800 MHz	256 KB	32 bit @ 533 MHz	32 bit Arm Cotex M4		-40 +125°C
STM32MP153DAB3	2	800 MHz	256 KB	32 bit @ 533 MHz	32 bit Arm Cotex M4		-40 +125°C
STM32MP157CAB3	2	650 MHz	256 KB	32 bit @ 533 MHz	32 bit Arm Cotex M4	3D: Vivante	-40 +125°C
STM32MP157DAB1	2	800 MHz	256 KB	32 bit @ 533 MHz	32 bit Arm Cotex M4	3D: Vivante	-20 +105°C

RAM memory bankEdit

Single DDR3L SDRAM memory bank. The following table reports the SDRAM specifications:

CPU connection	Multi-mode DDR controller (MMDC)
Size min	128 MB
Size max	1 GB
Width	32 bit
Speed	533 MHz

NOR flash bankEdit

NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the QUADSPI channel. and can act as boot memory. The following table reports the NOR flash specifications:

CPU connection	QUADSPI
Size min	16 MB
Size max	32 MB
Chip select	PB6
Bootable	Yes

NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.

NAND flash bankEdit

On board alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:

CPU connection	Raw NAND flash controller
Page size	512 byte, 2 kbyte or 4 kbyte
Size min	128 MB
Size max	2 GB
Width	8 bit
Chip select	PG9
Bootable	Yes

NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.

eMMC flash bankEdit

On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection	SDMMC2
Size min	4 GB
Size max	8 GB
Width	4/8 bit
SDHC	No
Bootable	Yes

NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus with to 4 bit

The eMMC and NAND flashes are surmounted, only one at time can be populated.

Memory mapEdit

For detailed information, please refer to chapter 2.5 “Memory organization” of the STM32MP1 Reference Manual (RM0436).

Power supply unitEdit

ETRA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.

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