Difference between revisions of "ETRA SOM/ETRA Hardware/General Information/Processor and memory subsystem"

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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |X.Y.Z
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |0.9.0
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Month Year
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |12/2020
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |TBD
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First Draft
 
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* SODIMM-DDR3 form-factor and connector with interfaces signals
 
* SODIMM-DDR3 form-factor and connector with interfaces signals
  
−
This chapter shortly describes the main Axel Lite components.
+
This chapter shortly describes the main ETRA components.
  
 
=== Processor Info ===
 
=== Processor Info ===
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| align="center" style="background:#f0f0f0;" |'''L2 Cache'''
 
| align="center" style="background:#f0f0f0;" |'''L2 Cache'''
 
| align="center" style="background:#f0f0f0;" |'''DDR3'''
 
| align="center" style="background:#f0f0f0;" |'''DDR3'''
 +
|'''MCU'''
 
| align="center" style="background:#f0f0f0;" |'''Graphics Acceleration'''
 
| align="center" style="background:#f0f0f0;" |'''Graphics Acceleration'''
−
| align="center" style="background:#f0f0f0;" |'''IPU'''
 
−
| align="center" style="background:#f0f0f0;" |'''VPU'''
 
 
| align="center" style="background:#f0f0f0;" |'''Temp grade'''
 
| align="center" style="background:#f0f0f0;" |'''Temp grade'''
 
|-
 
|-
−
| STM32MP151DAB3 || 1 ||800 MHz ||256 KB ||32 bit @ 533 MHz ||||1x ||1x ||-40 +125°C
+
| STM32MP151DAB3 || 1 ||800 MHz ||256 KB ||32 bit @ 533 MHz  
 +
|32 bit Arm Cotex M4||||-40 +125°C
 
|-
 
|-
−
| STM32MP153DAB3 || 2 ||800 MHz ||256 KB ||32 bit @ 533 MHz ||||2x ||2x || -40 +125°C
+
| STM32MP153DAB3 || 2 ||800 MHz ||256 KB ||32 bit @ 533 MHz  
 +
|32 bit Arm Cotex M4|||| -40 +125°C
 
|-
 
|-
−
| STM32MP157CAB3 || 2 ||650 MHz ||256 KB ||32 bit @ 533 MHz ||3D: Vivante ||2x ||2x || -40 +125°C
+
| STM32MP157CAB3 || 2 ||650 MHz ||256 KB ||32 bit @ 533 MHz  
 +
|32 bit Arm Cotex M4||3D: Vivante || -40 +125°C
 
|-
 
|-
 
|STM32MP157DAB1
 
|STM32MP157DAB1
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|256 KB
 
|256 KB
 
|32 bit @ 533 MHz
 
|32 bit @ 533 MHz
 +
|32 bit Arm Cotex M4
 
|3D: Vivante
 
|3D: Vivante
−
|
 
−
|
 
 
| -20 +105°C
 
| -20 +105°C
 
|-
 
|-
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=== RAM memory bank ===
 
=== RAM memory bank ===
  
−
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:
+
Single DDR3L SDRAM memory bank. The following table reports the SDRAM specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
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| '''CPU connection'''||Multi-mode DDR controller (MMDC)
 
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
 
|-
 
|-
−
| '''Size min'''||512 MB  
+
| '''Size min'''||128 MB  
 
|-
 
|-
−
| '''Size max'''||4 GB  
+
| '''Size max'''||1 GB  
 
|-
 
|-
−
| '''Width'''||64 bit  
+
| '''Width'''||32 bit  
 
|-
 
|-
 
| '''Speed'''||533 MHz  
 
| '''Speed'''||533 MHz  
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=== NOR flash bank ===
 
=== NOR flash bank ===
  
−
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:
+
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the QUADSPI channel. and can act as boot memory. The following table reports the NOR flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''||eCSPI channel 5
+
| '''CPU connection'''||QUADSPI
 
|-
 
|-
−
| '''Size min'''||8 MB  
+
| '''Size min'''||16 MB  
 
|-
 
|-
−
| '''Size max'''||64 MB  
+
| '''Size max'''||32 MB  
 
|-
 
|-
−
| '''Chip select'''||ECSPI5_SS0
+
| '''Chip select'''||PB6
 
|-
 
|-
 
| '''Bootable'''||Yes
 
| '''Bootable'''||Yes
 
|-
 
|-
 
|}
 
|}
 +
NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
  
 
=== NAND flash bank ===
 
=== NAND flash bank ===
  
−
On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
+
On board alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
  
 
{| class="wikitable" |  
 
{| class="wikitable" |  
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| '''Width'''||8 bit  
 
| '''Width'''||8 bit  
 
|-
 
|-
−
| '''Chip select'''||NANDF_CS0
+
| '''Chip select'''||PG9
 
|-
 
|-
 
| '''Bootable'''||Yes  
 
| '''Bootable'''||Yes  
 
|-
 
|-
 
|}
 
|}
 +
NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
  
 
=== eMMC flash bank ===
 
=== eMMC flash bank ===
−
 
+
On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications:
 
{| class="wikitable" |  
 
{| class="wikitable" |  
 
|-
 
|-
−
| '''CPU connection'''|| SDIO
+
| '''CPU connection'''|| SDMMC2
 
|-
 
|-
−
| '''Page size'''|| xxxxxx
+
| '''Size min'''||4 GB
 
|-
 
|-
−
| '''Size min'''||xxx MB
+
| '''Size max'''||8 GB
 
|-
 
|-
−
| '''Size max'''||xxx GB
+
| '''Width'''|| 4/8 bit
 
|-
 
|-
−
| '''Width'''|| xx bit
+
| '''SDHC'''||No
−
|-
 
−
| '''SDHC'''||
 
 
|-
 
|-
 
| '''Bootable'''||Yes  
 
| '''Bootable'''||Yes  
 
|-
 
|-
 
|}
 
|}
 +
NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus with to 4 bit
 +
 +
The eMMC and NAND flashes are surmounted, only one at time can be populated.
  
 
=== Memory map ===
 
=== Memory map ===
  
−
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.
+
For detailed information, please refer to chapter 2.5 “Memory organization” of the STM32MP1 Reference Manual (RM0436).
  
 
=== Power supply unit ===
 
=== Power supply unit ===

Revision as of 09:20, 28 December 2020

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History
Version Issue Date Notes
0.9.0 12/2020 First Draft
[TBD_link X.Y.Z] Month Year TBD
... ... ...


TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)

Processor and memory subsystem[edit | edit source]

The heart of ETRA module is composed by the following components:

  • STM32MP1 SoC application processor
  • Power supply unit
  • DDR3L memory banks
  • NOR and NAND flash banks
  • SODIMM-DDR3 form-factor and connector with interfaces signals

This chapter shortly describes the main ETRA components.

Processor Info[edit | edit source]

Processor # Cores Clock L2 Cache DDR3 MCU Graphics Acceleration Temp grade
STM32MP151DAB3 1 800 MHz 256 KB 32 bit @ 533 MHz 32 bit Arm Cotex M4 -40 +125°C
STM32MP153DAB3 2 800 MHz 256 KB 32 bit @ 533 MHz 32 bit Arm Cotex M4 -40 +125°C
STM32MP157CAB3 2 650 MHz 256 KB 32 bit @ 533 MHz 32 bit Arm Cotex M4 3D: Vivante -40 +125°C
STM32MP157DAB1 2 800 MHz 256 KB 32 bit @ 533 MHz 32 bit Arm Cotex M4 3D: Vivante -20 +105°C
Table: STM32MP1 models comparison

RAM memory bank[edit | edit source]

Single DDR3L SDRAM memory bank. The following table reports the SDRAM specifications:

CPU connection Multi-mode DDR controller (MMDC)
Size min 128 MB
Size max 1 GB
Width 32 bit
Speed 533 MHz

NOR flash bank[edit | edit source]

NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the QUADSPI channel. and can act as boot memory. The following table reports the NOR flash specifications:

CPU connection QUADSPI
Size min 16 MB
Size max 32 MB
Chip select PB6
Bootable Yes

NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.

NAND flash bank[edit | edit source]

On board alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:

CPU connection Raw NAND flash controller
Page size 512 byte, 2 kbyte or 4 kbyte
Size min 128 MB
Size max 2 GB
Width 8 bit
Chip select PG9
Bootable Yes

NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.

eMMC flash bank[edit | edit source]

On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection SDMMC2
Size min 4 GB
Size max 8 GB
Width 4/8 bit
SDHC No
Bootable Yes

NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus with to 4 bit

The eMMC and NAND flashes are surmounted, only one at time can be populated.

Memory map[edit | edit source]

For detailed information, please refer to chapter 2.5 “Memory organization” of the STM32MP1 Reference Manual (RM0436).

Power supply unit[edit | edit source]

ETRA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.


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