Difference between revisions of "ETRA SOM/ETRA Hardware/General Information/Processor and memory subsystem"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ||
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<section end="History" /> | <section end="History" /> | ||
<section begin="Body" /> | <section begin="Body" /> | ||
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== Processor and memory subsystem == | == Processor and memory subsystem == | ||
The heart of ETRA module is composed by the following components: | The heart of ETRA module is composed by the following components: | ||
| − | * | + | * STM32MP1 SoC application processor |
* Power supply unit | * Power supply unit | ||
* DDR3L memory banks | * DDR3L memory banks | ||
| Line 35: | Line 22: | ||
* SODIMM-DDR3 form-factor and connector with interfaces signals | * SODIMM-DDR3 form-factor and connector with interfaces signals | ||
| − | This chapter shortly describes the main | + | This chapter shortly describes the main ETRA components. |
=== Processor Info === | === Processor Info === | ||
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| align="center" style="background:#f0f0f0;" |'''L2 Cache''' | | align="center" style="background:#f0f0f0;" |'''L2 Cache''' | ||
| align="center" style="background:#f0f0f0;" |'''DDR3''' | | align="center" style="background:#f0f0f0;" |'''DDR3''' | ||
| + | | align="center" style="background:#f0f0f0;" |'''MCU''' | ||
| align="center" style="background:#f0f0f0;" |'''Graphics Acceleration''' | | align="center" style="background:#f0f0f0;" |'''Graphics Acceleration''' | ||
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| align="center" style="background:#f0f0f0;" |'''Temp grade''' | | align="center" style="background:#f0f0f0;" |'''Temp grade''' | ||
|- | |- | ||
| − | | | + | | STM32MP151 || 1 ||650MHz<br>800 MHz ||256 KB ||16/32 bit @ 533 MHz |
| + | |32 bit Arm Cortex M4 @209MHZ||||-40 +125°C | ||
|- | |- | ||
| − | | | + | | STM32MP153 || 2 ||650MHz<br>800 MHz ||256 KB ||16/32 bit @ 533 MHz |
| + | |32 bit Arm Cortex M4 @209MHZ|||| -40 +125°C | ||
|- | |- | ||
| − | | | + | | STM32MP157 || 2 ||650MHz<br>800 MHz ||256 KB ||16/32 bit @ 533 MHz |
| − | + | |32 bit Arm Cortex M4 @209MHZ||3D: Vivante GC Nano || -40 +125°C<br>-20 +105°C | |
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|+ align="bottom" style="caption-side: bottom" | Table: STM32MP1 models comparison | |+ align="bottom" style="caption-side: bottom" | Table: STM32MP1 models comparison | ||
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=== RAM memory bank === | === RAM memory bank === | ||
| − | + | Single DDR3L SDRAM memory bank. The following table reports the SDRAM specifications: | |
{| class="wikitable" | | {| class="wikitable" | | ||
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| '''CPU connection'''||Multi-mode DDR controller (MMDC) | | '''CPU connection'''||Multi-mode DDR controller (MMDC) | ||
|- | |- | ||
| − | | '''Size min'''|| | + | | '''Size min'''||128 MB |
|- | |- | ||
| − | | '''Size max'''|| | + | | '''Size max'''||1 GB |
|- | |- | ||
| − | | '''Width'''|| | + | | '''Width'''||16 bit |
|- | |- | ||
| '''Speed'''||533 MHz | | '''Speed'''||533 MHz | ||
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=== NOR flash bank === | === NOR flash bank === | ||
| − | NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the | + | NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the QUADSPI channel. and can act as boot memory. The following table reports the NOR flash specifications: |
{| class="wikitable" | | {| class="wikitable" | | ||
|- | |- | ||
| − | | '''CPU connection'''|| | + | | '''CPU connection'''||QUADSPI |
|- | |- | ||
| − | | '''Size min'''|| | + | | '''Size min'''||16 MB |
|- | |- | ||
| − | | '''Size max'''|| | + | | '''Size max'''||32 MB |
|- | |- | ||
| − | | '''Chip select'''|| | + | | '''Chip select'''||PB6 |
|- | |- | ||
| '''Bootable'''||Yes | | '''Bootable'''||Yes | ||
|- | |- | ||
|} | |} | ||
| + | NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. | ||
=== NAND flash bank === | === NAND flash bank === | ||
| − | On board | + | On board alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications: |
{| class="wikitable" | | {| class="wikitable" | | ||
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| '''Width'''||8 bit | | '''Width'''||8 bit | ||
|- | |- | ||
| − | | '''Chip select'''|| | + | | '''Chip select'''||PG9 |
|- | |- | ||
| '''Bootable'''||Yes | | '''Bootable'''||Yes | ||
|- | |- | ||
|} | |} | ||
| + | NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. | ||
=== eMMC flash bank === | === eMMC flash bank === | ||
| − | + | On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications: | |
{| class="wikitable" | | {| class="wikitable" | | ||
|- | |- | ||
| − | | '''CPU connection'''|| | + | | '''CPU connection'''|| SDMMC2 |
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|- | |- | ||
| − | | '''Size min'''|| | + | | '''Size min'''||4 GB |
|- | |- | ||
| − | | '''Size max'''|| | + | | '''Size max'''||8 GB |
|- | |- | ||
| − | | '''Width'''|| | + | | '''Width'''|| 4/8 bit |
|- | |- | ||
| − | | '''SDHC'''|| | + | | '''SDHC'''||No |
|- | |- | ||
| '''Bootable'''||Yes | | '''Bootable'''||Yes | ||
|- | |- | ||
|} | |} | ||
| + | NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus width to 4 bit | ||
| + | |||
| + | The eMMC and NAND flashes are overlapped, and can be alternatively populated. | ||
=== Memory map === | === Memory map === | ||
| − | For detailed information, please refer to chapter 2 “Memory | + | For detailed information, please refer to chapter 2.5 “Memory organization” of the STM32MP1 Reference Manual (RM0436). |
=== Power supply unit === | === Power supply unit === | ||
Latest revision as of 11:35, 8 January 2024
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Contents
Processor and memory subsystem[edit | edit source]
The heart of ETRA module is composed by the following components:
- STM32MP1 SoC application processor
- Power supply unit
- DDR3L memory banks
- NOR and NAND flash banks
- SODIMM-DDR3 form-factor and connector with interfaces signals
This chapter shortly describes the main ETRA components.
Processor Info[edit | edit source]
| Processor | # Cores | Clock | L2 Cache | DDR3 | MCU | Graphics Acceleration | Temp grade |
| STM32MP151 | 1 | 650MHz 800 MHz |
256 KB | 16/32 bit @ 533 MHz | 32 bit Arm Cortex M4 @209MHZ | -40 +125°C | |
| STM32MP153 | 2 | 650MHz 800 MHz |
256 KB | 16/32 bit @ 533 MHz | 32 bit Arm Cortex M4 @209MHZ | -40 +125°C | |
| STM32MP157 | 2 | 650MHz 800 MHz |
256 KB | 16/32 bit @ 533 MHz | 32 bit Arm Cortex M4 @209MHZ | 3D: Vivante GC Nano | -40 +125°C -20 +105°C |
RAM memory bank[edit | edit source]
Single DDR3L SDRAM memory bank. The following table reports the SDRAM specifications:
| CPU connection | Multi-mode DDR controller (MMDC) |
| Size min | 128 MB |
| Size max | 1 GB |
| Width | 16 bit |
| Speed | 533 MHz |
NOR flash bank[edit | edit source]
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the QUADSPI channel. and can act as boot memory. The following table reports the NOR flash specifications:
| CPU connection | QUADSPI |
| Size min | 16 MB |
| Size max | 32 MB |
| Chip select | PB6 |
| Bootable | Yes |
NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
NAND flash bank[edit | edit source]
On board alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
| CPU connection | Raw NAND flash controller |
| Page size | 512 byte, 2 kbyte or 4 kbyte |
| Size min | 128 MB |
| Size max | 2 GB |
| Width | 8 bit |
| Chip select | PG9 |
| Bootable | Yes |
NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
eMMC flash bank[edit | edit source]
On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications:
| CPU connection | SDMMC2 |
| Size min | 4 GB |
| Size max | 8 GB |
| Width | 4/8 bit |
| SDHC | No |
| Bootable | Yes |
NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus width to 4 bit
The eMMC and NAND flashes are overlapped, and can be alternatively populated.
Memory map[edit | edit source]
For detailed information, please refer to chapter 2.5 “Memory organization” of the STM32MP1 Reference Manual (RM0436).
Power supply unit[edit | edit source]
ETRA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
