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The Vivado repository allows to:
* track hardware/fpga related sources/configuration
* reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts. Development kit TCL scripts supported are as followthe following one:
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* clone the repository:
<syntaxhighlight lang="bash">
</syntaxhighlight>
or you can clone the Vivado repository when you clone Petalinux repository
<syntaxhighlight lang="bash">
</syntaxhighlight>
* (only once as first tools setup) copy ''Bora'' hardware definition into Vivado installation.path:
<syntaxhighlight lang="bash">
cp -r boards/ /opt/Xilinx/2021.2/Vivado/2021.2/data/
</syntaxhighlight>
* lunch Vivado Design Suite with the following commandcommands and parameters:
<syntaxhighlight lang="bash">
source /opt/Xilinx/2021.2/Vivado/2021.2/settings64.sh
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
</syntaxhighlight>
* at the end of the bitstream build process, the script automatically exports the Xilinx Support Archive ('''XSA''') hardwaredesign** The the Vivado project ready for customization through Vivado GUI is available into <code>vivado/bora.xpr</code>is ready for customization through the Vivado GUI** The the bitstream file is now present infiles are
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bit</code>
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bin</code>
** The the hardware export, ready for import into Petalinux, is available in design file <code>vivado/bora.xsa</code>is ready for the import into Petalinux
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