a000298_approval, dave_user
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→GUI based procedure
==GUI based procedure==
{{ImportantMessage|text=The following procedure is detailed for Bora boardmake use of ambient variables to address all our boards.<br>For BoraX board please replace:*<code>bora_wrapperDefine the correct ones according the target SoM.v</code> with <code>borax_wrapper.v</codebr>*<code>bora_pinout.xdc</code> with <code>borax_pinout.xdc</code>For Bora SoM use:*<code>bora_timings.xdc</code> with <code>borax_timings.xdcexport BORA_SOM Bora</code>*<code>export BASE_NAME bora.sdk</code> with <code>borax.sdk</code>*<code>bora_wrapper.bit</code> with <code>borax_wrapper.bitexport U-BOOT_PS7_DIR bora</code>.For BoraLite board please replaceSoM use:*<code>boraexport BORA_SOM BoraLite</code> with *<code>export BASE_NAME boralite</code>*<code>bora_wrapper.v</code> with <code>boralite_wrapper.vexport U-BOOT_PS7_DIR bora</code>*<code>bora_pinout.xdc</code> with <code>boralite_pinout.xdc</code>For BoraX SoM use:*<code>bora_timings.xdc</code> with <code>boralite_timings.xdcexport BORA_SOM BoraX</code>*<code>bora.sdk</code> with <code>boralite.sdkexport BASE_NAME borax</code>*<code>bora_wrapper.bitexport U-BOOT_PS7_DIR borax</code> with <code>boralite_wrapper.bit</code>.
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*from the start page click on ''Create New Project''
*click ''Next''
*select the directory build project, insert the name of the project ''Project Name<prj_name>'' and click ''Next''
*select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''
*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA${BORA_SOM}'' ''BORAX'' depending on target SOM and click ''Next''
*check the summary page and click ''Finish''
*For the block design there are two possible ways:
***select ''Add sources'' from the ''Flow Navigator''
***click on ''Add or create design sources''
***select Add Files and add <code><bora_repo>/bd/bora${BASE_NAME}/bora${BASE_NAME}.bd</code>
***check that the option ''Copy sources into project'' is disabled and click finish
**Create a new block design:
***click on ''Create Block Design'' from the ''Flow Navigator''
***insert ''bora${BASE_NAME}'' as ''Design name'' and click ''OK''
***this creates a new block design. From the Diagram tab, add a new IP:
****click the ''Add IP'' side button, or
****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually
***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
***from the sources tab, select the BORA block design <code>bora${BASE_NAME}.bd</code> as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
***on the next window, select ''Let Vivado menage wrapper and auto-update'' and click ''OK''
***this creates the Verilog file <code>bora_wrapper${BASE_NAME}_wrapper.v</code>. If this file is not automatically included in the project, add it using the ''Add sources'' option
****select Add or create design sources and click ''Next''
****select the <code>bora_wrapper>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/</code> directory
*select ''Add sources'' and click on ''Add or create constraints''
*select the <code>bora_pinout${BASE_NAME}_pinout.xdc</code> and <code>bora_timings${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository
*check that the option ''Copy constraints'' ''files into project'' is disabled and click finish
*create the synthesis, implementation and bitstream clicking ''Generate Bitstream'' from the ''Flow Navigator'' and wait the completion of the operation
*once completed, select ''Open Implemented Design''
*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''
*select the <code>generate_binary_bitstream.tcl</code> file from the <code>scripts </code> directory from the BORA repository*The bitstream file is now present in <code>.bit<project_directory>/code> and <codeprj_name>.binruns/impl_1/${BASE_NAME}_wrapper.bit</code> format at and <code><bora_repoproject_directory>/vivado/bora<prj_name>.runs/impl_1/bora_wrapper${BASE_NAME}_wrapper.bin</code>.
*Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora:
:<code>cp <project_directory>/bora<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/ip/bora_processing_system7_0_0<prj_name>_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora${U-BOOT_PS7_DIR}/</code>Follow [[Building_U-Boot_(BELK/BXELK) | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.
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