*generate the PS configuration files to be used on with U-boot SPL build

{{ImportantMessage|text=The following procedure is detailed for Bora board. <br>For BoraX board please replace:*<code>bora_FSBLbora</code> with <code>borax_FSBLborax</code>*<code>bora_wrapper_hw_platform_0recreate_project_bora_BASE</code> with <code>borax_wrapper_hw_platform_0recreate_project_borax_BASE</code>For BoraLite board please replace:*<code>bora.sdk</code> with <code>borax.sdkboralite</code>*<code>bora_wrapper.bitrecreate_project_bora_BASE</code> with <code>borax_wrapper.bitrecreate_project_boralite_BASE</code>.

vivado -mode tcl -source scripts/recreate_project_bora_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*the <code>build_project</code> script allows user to select BORA or BORAX target*at At the end of the bitstream build process, the <code>build_projectbuild_project_*</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*For BELK 3.0.2 or older and for BXELK 1.0.1 or older: please follow the [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#FSBL_project_build | FSBL build instructions]]*For BELK 4.0.0 or newer and BXELK 2.0.0 or newer, by By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.

:<code>cp $PROJ_DIR<bora_repo>/vivado/bora.srcs/sources_1/bd/bora/ip/bora_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora/</code>

{{ImportantMessage|text=The following procedure is detailed for Bora board. <br>For BoraX board please replace:

*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA'' or ''BORAX'' depending on target SOM and click ''Next''

*in For the block design there are two possible ways:**Add the existing BD within the repo: ***select ''Add sources'' from the ''Flow Navigator''***click on ''Add or create design sources''***select Add Files and add <code><bora_repo>/bd/bora/bora.bd</code>***check that the Vivado GUI option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design'' from the ''Flow Navigator''***insert ''bora'' (or ''borax'' in case of BoraX board) as ''Design name'' and click ''OK''***this creates a new block design. From the Diagram tab, add a new IP:****click the ''Add IP'' side button, or****click ''Add IP'' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar***check that ''Apply Board Preset'' is selected and click ''OK''****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins**for '''BELK <= 3.0.2''' and '''BXELK <= 1.0.1''': the default settings automatically creates also connections for the UART_0 and CAN_0 interfaces**for '''BELK-4.0.0''' and '''BXELK-2.0.0''': UART_0 and CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually***alternatively, execute the following commands from tcl console:<pre>create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/UART_0] [get_bd_intf_ports UART_0]create_bd_intf_port -mode Master -vlnv xilinx.com:interface:can_rtl:1.0 CAN_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/CAN_0] [get_bd_intf_ports CAN_0]</pre>*manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design***from the sources tab, select the BORA/BORAX block design (<code>bora.bd</code> for Bora, <code>borax.bd</code> for BoraX) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''***on the next window, select ''Copy generated Let Vivado menage wrapperand auto-update'' to allow user edits and click ''OK''***this creates the Verilog file (<code>bora_wrapper.v</code> for Bora, <code>borax_wrapper.v</code> for BoraX). If this file is not automatically included in the project, add it using the ''Add sources'' option****select Add or create design sources and click ''Next''****select the <code>bora_wrapper.v</code> file from the <code><prj_name>.srcs/sources_1/bd/bora/hdl/</code> directory 

*check that the option ''Copy constraints'' '' files into project '' is enableddisabled and click finish

*select ''File -> Export -> Export Hardware''*on the next window, enable ''Include Bitstream'' and click ''OK''*now launch the SDK session to generate the FSBL, clicking on ''File -> Launch SDK''*For '''BELK <= 3.0.2''' and '''BXELK <= 1.0.1''' : please follow the [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#FSBL_project_build | FSBL build instructions]]*For '''BELK-4.0.0''' and '''BXELK-2.0.0''' there is no need to build FSBL. Instead PS configurations files are used to build U-boot binaries if necessary.**Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora::<code>cp $PROJ_DIR<project_directory>/bora.srcs/sources_1/bd/bora/ip/bora_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora/</code>:*Follow [[Building_U-Boot_(BELK/BXELK) | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.