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==Introduction==
BELK/BXELK provides an example Vivado project for BORA/BORAX /BORALITE boards. This project allows to:*generate FSBL binary imagethe PS configuration files to be used on U-boot SPL build
*generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).
[[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]]
[[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORAX example project]]
[[File:Boralite-default-vivado-project.png|center|thumb|400x400px]]
This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.
*assuming that a local repository has not been created, clone the remote BORA git repository:
*:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
*copy the <code><bora_repo>/boards/</code> directory to <code><vivado_install_dir>/data/boards/</code> :
<pre>
cd <bora_repo>
sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/
</pre>
*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.}}:
<pre>
. /opt/Xilinx/Vivado/<Vivado_version>/settings64.sh
vivado -mode tcl -source build_projectscripts/recreate_project_bora_BASE.tcl -notrace -tclargs "-bitstream"
</pre>
*the <code>build_project</code> script allows user to select BORA or BORAX target