a000298_approval, dave_user
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*start the Zynq development server and login into the system
*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
*copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_201x.y_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :
<pre>
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/201x.y<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/201x.y/data/boards/board_parts/zynq/
</pre>
*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/201x.y/settings32.sh</code>}}:
*this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins
**for '''BELK <= 3.0.2''' and '''BXELK <= 1.0.1''': the default settings automatically creates also connections for the UART_0 and CAN_0 interfaces
**for '''BELK-4.0.0''' and '''BXELK-2.0.0''': UART_0 and CAN_0 connections must be manually created by :***right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>.The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually***alternatively, execute the following commands from tcl console:<pre>create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/UART_0] [get_bd_intf_ports UART_0]create_bd_intf_port -mode Master -vlnv xilinx.com:interface:can_rtl:1.0 CAN_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/CAN_0] [get_bd_intf_ports CAN_0]</pre>
*manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
*from the sources tab, select the BORA/BORAX block design (<code>bora.bd</code> for Bora, <code>borax.bd</code> for BoraX) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
