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→GUI based procedure
==GUI based procedure==
The following procedure is detailed for Bora board. For BoraX board please replace:
*bora_wrapper.v with borax_wrapper.v
*bora_pinout.xdc with borax_pinout.xdc
*bora_timings.xdc with borax_timings.xdc
*bora_FSBL with borax_FSBL
*bora.sdk with borax.sdk
*bora_FSBL.elf with borax_FSBL.elf
*bora_wrapper.bit with borax_wrapper.bit.
*start the Zynq development server and login into the system
*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
*check the summary page and click ''Finish''
*in the Vivado GUI click on ''Create Block Design'' from the ''Flow Navigator''
*this step is board dependent:**for Bora: insert ''bora'' as (or ''Design name'borax' and click ''OK''**for in case of BoraX: insert ''borax'' board) as ''Design name'' and click ''OK''
*this creates a new block design. From the Diagram tab, add a new IP:
**click the ''Add IP'' side button, or
*this creates the Verilog file (<code>bora_wrapper.v</code> for Bora, <code>borax_wrapper.v</code> for BoraX). If this file is not automatically included in the project, add it using the ''Add sources'' option
**select Add or create design sources and click ''Next''
**this step is board dependent***for Bora: select the <code>bora_wrapper.v</code> file from the <code><prj_name>.srcs/sources_1/bd/bora/hdl/</code> directory***for BoraX: select the <code>borax_wrapper.v</code> file from the <code><prj_name>.srcs/sources_1/bd/borax/hdl/</code> directory
*select ''Add sources'' and click on ''Add or create constraints''
*this step is board dependent**for Bora: select the <code>bora_pinout.xdc</code> and <code>bora_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository**for BoraX: select the <code>borax_pinout.xdc</code> and <code>borax_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository
*check that the option ''Copy constraints'' files into project is enabled
*create the synthesis, implementation and bitstream clicking ''Generate Bitstream'' from the ''Flow Navigator'' and wait the completion of the operation
*once the Xilinx SDK is ready, perform the following operations from the GUI:
**Click on ''File -> New -> Application Project''
**this step is board dependent***for Bora: select the Project Name: <code>bora_FSBL</code>***for BoraX: select the Project Name: <code>borax_FSBL</code>
**Click ''Next''
**Select ''Template: Zynq FSBL''
**Click on ''Finish''
**this step is board dependent
***for Bora: apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..***for BoraX: apply the patch, right-clicking on borax_FSBL in Project Explorer and then clicking on Team -> Apply Patch..*this step is board dependent**for Bora: from ''Browse...'' open the file <code><bora_repo>/patch/belk-sd-boot.patch</code>**for BoraX: from ''Browse...'' open the file <code><bora_repo>/patch/belkx-sd-boot.patch</code>
**Click ''Next''
**this step is board dependent***for Bora: Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''bora_FSBL -> src''***for BoraX: Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''borax_FSBL -> src''
**Click ''Next''
**Check that the patch is correctly applied to the source code and click on ''Finish''
**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
***this step is board dependent****for Bora: apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under ''bora_wrapper_hw_platform_0''****for BoraX: apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under ''borax_wrapper_hw_platform_0''***this step is board dependent****for Bora: apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under ''bora_wrapper_hw_platform_0''****for BoraX: apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under ''borax_wrapper_hw_platform_0''
*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
**this step is board dependent
***for Bora: manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin</code>***for BoraX: manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/borax.sdk/SDK/SDK_Export/borax_FSBL/Debug/borax_FSBL.elf $PROJ_DIR/borax.sdk/SDK/SDK_Export/borax_FSBL/Debug/borax_FSBL.bin</code>**this step is board dependent***for Bora: configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>bora_FSBL</code> project and select ''C/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''***for BoraX: configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>borax_FSBL</code> project and select ''C/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot:
**this step is board dependent
***for Bora: select configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>bora_FSBL</code> project in and select ''C/C++ Build Settings''Project Explorerand add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot):**for BoraXBora: select the <code>borax_FSBLbora_FSBL</code> project in ''Project Explorer''
**click on ''Xilinx Tools -> Create Zynq Boot Image''
*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.
*otherwise, select ''Create new BIF file'' and set the output path and in ''Boot image partitions'' add the following files:
**<code>u-boot.elf</code>, which is the compiled U-Boot with <code>.elf</code> extension (<u>''Partition Type'' must be ''Datafile''</u>)
*in ''Output path'', select the path for the <code>BOOT.bin</code> file
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