*generate FSBL binary image

*generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).

[[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]]

[[File:TBD.png|thumb|center|400px|Block diagram of BORAX example project]]

This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.