*generate FSBL binary image

*generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following picture).

TBD

This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.

It is assumed that the Zynq development environment has been set up properly (see [[Build_system_(BELK)|this page]] for more details).

==Command line based procedure==

*start the Zynq development server and login into the system