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→GUI based procedure
*on the next window, select ''Copy generated wrapper'' to allow user edits and click ''OK''
*this creates the Verilog <code>bora_wrapper.v</code> file. If this file is not automatically included in the project, add it using the ''Add sources'' option
**select Add or create design sources and click ''Next''**select the <code>bora_wrapper.v </code> file from the <code><prj_name>.srcs/sources_1/bd/bora/hdl/ </code> directory*select ''Add sources '' and click on ''Add or create constraints''*select the <code>bora_pinout.xdc </code> and <code>bora_timings.xdc </code> files from the <code>constr </code> directory of the BORA repository*check that the option ''Copy constraints '' files into project is enabled*create the synthesis, implementation and bitstream clicking ''Generate Bitstream '' from the ''Flow Navigator '' and wait the completion of the operation*once completed, select ''Open Implemented Design''*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''*select the <code>generate_binary_bitstream.tcl </code> file from the scripts directory from the BORA repository*select ''File -> Export -> Export Hardware''*on the next window, enable ''Include Bitstream '' and click ''OK''*now launch the SDK session to generate the FSBL, clicking on ''File -> Launch SDK''
*once the Xilinx SDK is ready, perform the following operations from the GUI:
**Click on ''File -> New -> Application Project''**Select the Project Name: <code>bora_FSBL</code>**Click Next**Select Template: Zynq FSBL**Click on Finish**Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
From Browse... open the file <bora_repo>/patch/belk-sd-boot.patch
**Click Next
Select Apply the patch to the selected file, folder or project: and select main.c from bora_FSBL -> src
**Click Next**Check that the patch is correctly applied to the source code and click on ''Finish''*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
**manually launch the command: arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin**configure the automatic binary generation on project build. In Project Explorer, right-click on “bora_FSBL” project and select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps
*create the BOOT.bin image (single file including FSBL, FPGA and U-boot for uSD boot:
**select the bora_FSBL project in Project Explorer**click on Xilinx Tools -> Create Zynq Boot Image*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.
*otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
**bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloader**bora_wrapper.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)**u-boot.elf, which is the compiled U-Boot with .elf extension (Partition Type must be Datafile)*in Output path, select the path for the BOOT.bin file