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==Creating and building a Zynq project for BORA /BORAX using the command line==
It is assumed that the development environment has been set up properly as described [[Build_system_(BELK)|here]].
*in ''Output path'', select the path for the <u>BOOT.bin</u> file.
==Creating and building a Zynq project for BORA/BORAX using the Vivado GUI==
start the Zynq development server and login into the system
assuming that a local repository has not been created, clone the remote BORA git repository:
git clone git@git.dave.eu:dave/bora/bora.git
copy the <bora_repo>/boards/board_parts/zynq/BELK_2.2.0 directory to <vivado_2014.4_install_dir>/data/boards/board_parts/zynq/ :
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
launch Vivado v2014.4 and from the start page click on Create New Project
click Next
select the directory build project, insert the name of the project Project Name and click Next
select RTL Project, enable Do not specify sources at this time and click Next
on the Default Part form, click on the Boards button to filter the available boards. Select BELK 2.2.0 and click Next
check the summary page and click Finish
in the Vivado GUI click on Create Block Design from the Flow Navigator
insert bora as Design name and click OK
this creates a new block design. From the Diagram tab, add a new IP:
click the Add IP side button, or
click Add IP on the upper suggestions bar
double click on ZYNQ7 Processing System
this adds the IP that models the PL component of Zynq. Launch Run Block Automation from the upper suggestions bar
check that Apply Board Preset is selected and click OK
this applies the default settings for BORA and creates the I/O ports for the DDR and MIO pins and for the UART_0 and CAN_0 interfaces
manually connect the FCLK_CLK0 signal to M_AXI_GP0_ACLK and save the block design
from the sources tab, select the BORA block design (bora.bd) as Design Sources and from the context menu select Create HDL Wrapper
on the next window, select Copy generated wrapper to allow user edits and click OK
this creates the Verilog bora_wrapper.v file. If this file is not automatically included in the project, add it using the Add sources option
select Add or create design sources and click Next
select the bora_wrapper.v file from the <prj_name>.srcs/sources_1/bd/bora/hdl/ directory
select Add sources and click on Add or create constraints
select the bora_pinout.xdc and bora_timings.xdc files from the constr directory of the BORA repository
check that the option Copy constraints files into project is enabled
create the synthesis, implementation and bitstream clicking Generate Bitstream from the Flow Navigator and wait the completion of the operation
once completed, select Open Implemented Design
create the binary bitstream running the tcl script provided with the BORA repository. Launch Tools -> Run Tcl Script
select the generate_binary_bitstream.tcl file from the scripts directory from the BORA repository
select File -> Export -> Export Hardware
on the next window, enable Include Bitstream and click OK
now launch the SDK session to generate the FSBL, clicking on File -> Launch SDK
once the Xilinx SDK is ready, perform the following operations from the GUI:
Click on File -> New -> Application Project
Select the Project Name: bora_FSBL
Click Next
Select Template: Zynq FSBL
Click on Finish
Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
From Browse... open the file <bora_repo>/patch/belk-sd-boot.patch
Click Next
Select Apply the patch to the selected file, folder or project: and select main.c from bora_FSBL -> src
Click Next
Check that the patch is correctly applied to the source code and click on Finish
the FSBL (ELF file) is built automatically
create the binary from the FSBL ELF chosing one of the following options:
manually launch the command: arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin
configure the automatic binary generation on project build. In Project Explorer, right-click on “bora_FSBL” project and select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps
create the BOOT.bin image (single file including FSBL, FPGA and U-boot for uSD boot:
select the bora_FSBL project in Project Explorer
click on Xilinx Tools -> Create Zynq Boot Image
if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.
otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloader
bora_wrapper.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)
u-boot.elf, which is the compiled U-Boot with .elf extension (Partition Type must be Datafile)
in Output path, select the path for the BOOT.bin file