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<section begin=BELK/>=Introduction=Creating and building example Vivado project==
BELK/BXELK provides an example Vivado project for BORA/BORAX/BORALITE boards. This project allows to:
*generate the PS configuration files to be used with U-boot SPL build
This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.
The project is stored is a git repository, as described [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]].
It is assumed that the Zynq development environment has been set up properly (see [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system|this page]] for more details).
===Command line based procedure===
{{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>
Define the correct ones according the target SoM.<br>
For Bora SoM use:
*<code>export RECREATE_PRJ recreate_prj_bora_BASE.tcl</code>*<code>export PRJ_FOLDER BASE_NAME=bora</code>*<code>export BITSTREAM_FILE bora_wrapper</code>*<code>export PS7_FOLDER bora_processing_system7_0_0</code>*<code>export U-BOOT_PS7_FOLDER UBOOT_PS7_DIR=bora</code>
For BoraLite SoM use:
*<code>export RECREATE_PRJ recreate_prj_boralite_BASE.tcl</code>*<code>export PRJ_FOLDER BASE_NAME=boralite</code>*<code>export BITSTREAM_FILE boralite_wrapper</code>*<code>export PS7_FOLDER boralite_processing_system7_0_0</code>*<code>export U-BOOT_PS7_FOLDER UBOOT_PS7_DIR=bora</code>
For BoraX SoM use:
*<code>export RECREATE_PRJ recreate_prj_borax_BASE.tcl</code>*<code>export PRJ_FOLDER BASE_NAME=borax</code>*<code>export BITSTREAM_FILE borax_wrapper</code>*<code>export PS7_FOLDER borax_processing_system7_0_0</code>*<code>export U-BOOT_PS7_FOLDER UBOOT_PS7_DIR=borax</code>
}}
<pre>
. /opt/Xilinx/Vivado/<Vivado_version>/settings64.sh
vivado -mode tcl -source scripts/recreate_prj_${RECREATE_PRJBASE_NAME} _BASE.tcl -notrace -tclargs "gen_bitstream"
</pre>
*At the end of the bitstream build process, the <code>build_prj_*</code> script allows to automatically export hardware and lauch SDK.
*The bitstream file is now present in <code><bora_repo>/vivado/${PRJ_FOLDERBASE_NAME}.runs/impl_1/${BITSTREAM_FILEBASE_NAME}_wrapper.bit</code> and <code><bora_repo>/vivado/${PRJ_FOLDERBASE_NAME}.runs/impl_1/${BITSTREAM_FILEBASE_NAME}_wrapper.bin</code>.
*By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.
**Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora:
:<code>cp <bora_repo>/bd/${PRJ_FOLDERBASE_NAME}/ip/${PS7_FOLDERBASE_NAME}_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/${U-BOOT_PS7_FOLDERUBOOT_PS7_DIR}/</code>:*Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot_(BELK/BXELK) Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.
:**The PS configurations are the same for Bora and BoraLite boards.
===GUI based procedure==={{ImportantMessage|text=The following procedure is detailed for Bora boardmake use of ambient variables to address all our boards.<br>For BoraX board please replace:*<code>bora_wrapperDefine the correct ones according the target SoM.v</code> with <code>borax_wrapper.v</codebr>*<code>bora_pinout.xdc</code> with <code>borax_pinout.xdc</code>For Bora SoM use:*<code>bora_timings.xdc</code> with <code>borax_timings.xdcexport BORA_SOM=Bora</code>*<code>export BASE_NAME=bora.sdk</code> with <code>borax.sdk</code>*<code>bora_wrapper.bitexport UBOOT_PS7_DIR=bora</code> with <code>borax_wrapper.bit</code>.For BoraLite board please replaceSoM use:*<code>boraexport BORA_SOM=BoraLite</code> with *<code>export BASE_NAME=boralite</code>*<code>bora_wrapper.v</code> with <code>boralite_wrapper.vexport UBOOT_PS7_DIR=bora</code>*<code>bora_pinout.xdc</code> with <code>boralite_pinout.xdc</code>For BoraX SoM use:*<code>bora_timings.xdc</code> with <code>boralite_timings.xdcexport BORA_SOM=BoraX</code>*<code>bora.sdk</code> with <code>boralite.sdkexport BASE_NAME=borax</code>*<code>bora_wrapper.bitexport UBOOT_PS7_DIR=borax</code> with <code>boralite_wrapper.bit</code>.
}}
*from the start page click on ''Create New Project''
*click ''Next''
*select the directory build project, insert the name of the project ''Project Name<prj_name>'' and click ''Next''
*select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''
*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA${BORA_SOM}'' ''BORAX'' depending on target SOM and click ''Next''
*check the summary page and click ''Finish''
*For the block design there are two possible ways:
***select ''Add sources'' from the ''Flow Navigator''
***click on ''Add or create design sources''
***select Add Files and add <code><bora_repo>/bd/bora${BASE_NAME}/bora${BASE_NAME}.bd</code>
***check that the option ''Copy sources into project'' is disabled and click finish
**Create a new block design:
***click on ''Create Block Design'' from the ''Flow Navigator''
***insert ''bora${BASE_NAME}'' as ''Design name'' and click ''OK''
***this creates a new block design. From the Diagram tab, add a new IP:
****click the ''Add IP'' side button, or
****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually
***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
***from the sources tab, select the BORA block design <code>bora${BASE_NAME}.bd</code> as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
***on the next window, select ''Let Vivado menage wrapper and auto-update'' and click ''OK''
***this creates the Verilog file <code>bora_wrapper${BASE_NAME}_wrapper.v</code>. If this file is not automatically included in the project, add it using the ''Add sources'' option
****select Add or create design sources and click ''Next''
****select the <code>bora_wrapper>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/</code> directory
*select ''Add sources'' and click on ''Add or create constraints''
*select the <code>bora_pinout${BASE_NAME}_pinout.xdc</code> and <code>bora_timings${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository
*check that the option ''Copy constraints'' ''files into project'' is disabled and click finish
*create the synthesis, implementation and bitstream clicking ''Generate Bitstream'' from the ''Flow Navigator'' and wait the completion of the operation
*once completed, select ''Open Implemented Design''
*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''
*select the <code>generate_binary_bitstream.tcl</code> file from the <code>scripts </code> directory from the BORA repository*The bitstream file is now present in <code>.bit<project_directory>/code> and <codeprj_name>.binruns/impl_1/${BASE_NAME}_wrapper.bit</code> format at and <code><bora_repoproject_directory>/vivado/bora<prj_name>.runs/impl_1/bora_wrapper${BASE_NAME}_wrapper.bin</code>.
*Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora:
:<code>cp <project_directory>/bora<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/ip/bora_processing_system7_0_0<prj_name>_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora${UBOOT_PS7_DIR}/</code>Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot_(BELK/BXELK) Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.
-----
{{notelist}}
=== Downloading the bitstream to the device ===
Once the bitstream is ready, U-Boot itself can be used to download it onto the device. There are other options, however. For more details, please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot#Introduction|this section]].
=== Helloworld from UART0 ===
Using the FPGA bitstream previously created, it is possible to use serial tty port on Linux. The serial port is mapped to <code>/dev/ttyPS1</code> (this is because <code>/dev/ttyPS0</code> is the console mapped to UART1).
<pre>
dvdk@vagrant-ubuntu-trusty-64:~/bora/rfs/belk/home/root$ source ~/env.sh dvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0
</pre>
The program executed print out the msg string on the serial console and on <code>/dev/ttyPS1</code> port.
<section end=BELK/>