!BELK /BXELK version

|{{oldid|9008|2.0.1}}

<section begin=BELK/>=Introduction=Creating and building example Vivado project==BELK/BXELK provides an example Vivado project for BORA/BORAX /BORALITE boards. This project allows to:*generate FSBL binary imagethe PS configuration files to be used with U-boot SPL build

The project is stored is a git repository, as described [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]].

It is assumed that the Zynq development environment has been set up properly (see [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system|this page]] for more details).

===Command line based procedure==={{ImportantMessage|text=The following procedure is detailed for Bora boardmake use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM. <br>For BoraX board please replaceBora SoM use:*<code>bora_FSBLexport BASE_NAME=bora</code> with *<code>borax_FSBLexport UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>bora_wrapper_hw_platform_0</code> with <code>borax_wrapper_hw_platform_0export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora.sdk</code> with For BoraX SoM use:*<code>export BASE_NAME=borax.sdk</code>*<code>bora_wrapper.bit</code> with <code>borax_wrapper.bitexport UBOOT_PS7_DIR=borax</code>.

*copy the <code><bora_repo>/boards/</code> directory to <code><vivado_install_dir>/data/boards/</code> :

*enter the git directory and launch the following command to set the project directory*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstreamgen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

vivado -mode tcl -source build_projectscripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*the <code>build_project</code> script allows user to select BORA or BORAX target*at At the end of the bitstream build process, the <code>build_projectbuild_prj_*</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*For BELK 3The bitstream file is now present in <code><bora_repo>/vivado/${BASE_NAME}.0runs/impl_1/${BASE_NAME}_wrapper.2 or older bit</code> and for BXELK 1<code><bora_repo>/vivado/${BASE_NAME}.0runs/impl_1/${BASE_NAME}_wrapper.1 or older: please follow the [[Creating_and_building_example_Vivado_project_(BELKbin</BXELK)#FSBL_project_build | FSBL build instructions]]code>.*For BELK 4.0.0 or newer and BXELK 2.0.0 or newer, by By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.

:<code>cp $PROJ_DIR/bora.srcs/sources_1<bora_repo>/bd/bora${BASE_NAME}/ip/bora_processing_system7_0_0${BASE_NAME}_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora${UBOOT_PS7_DIR}/</code>:*Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot_(BELK/BXELK) Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.:**The PS configurations are the same for Bora and BoraLite boards.

===GUI based procedure==={{ImportantMessage|text=The following procedure is detailed for Bora boardmake use of ambient variables to address all our boards. For BoraX board please replace:*<codebr>bora_wrapperDefine the correct ones according the target SoM.v</codebr> with For Bora SoM use:*<code>borax_wrapper.vexport BORA_SOM=Bora</code>*<code>bora_pinout.xdcexport BASE_NAME=bora</code> with *<code>borax_pinout.xdcexport UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>bora_timings.xdc</code> with <code>borax_timings.xdcexport BORA_SOM=BoraLite</code>*<code>bora_FSBL</code> with <code>borax_FSBLexport BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora.sdk</code> with For BoraX SoM use:*<code>borax.sdkexport BORA_SOM=BoraX</code>*<code>bora_FSBL.elf with <code>borax_FSBL.elfexport BASE_NAME=borax</code>*<code>bora_wrapper.bit</code> with <code>borax_wrapper.bitexport UBOOT_PS7_DIR=borax</code>.

*select the directory build project, insert the name of the project ''Project Name<prj_name>'' and click ''Next''

*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA${BORA_SOM}'' or ''BORAX'' depending on target SOM and click ''Next''

*in For the block design there are two possible ways:**Add the existing BD within the repo: ***select ''Add sources'' from the ''Flow Navigator''***click on ''Add or create design sources''***select Add Files and add <code><bora_repo>/bd/${BASE_NAME}/${BASE_NAME}.bd</code>***check that the Vivado GUI option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design'' from the ''Flow Navigator''***insert ''bora${BASE_NAME}'' (or ''borax'' in case of BoraX board) as ''Design name'' and click ''OK''***this creates a new block design. From the Diagram tab, add a new IP:****click the ''Add IP'' side button, or****click ''Add IP'' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar***check that ''Apply Board Preset'' is selected and click ''OK''****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins**for '''BELK <= 3.0.2''' and '''BXELK <= 1.0.1''': the default settings automatically creates also connections for the UART_0 and CAN_0 interfaces**for '''BELK-4.0.0''' and '''BXELK-2.0.0''': UART_0 and CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually***alternatively, execute the following commands from tcl console:<pre>create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/UART_0] [get_bd_intf_ports UART_0]create_bd_intf_port -mode Master -vlnv xilinx.com:interface:can_rtl:1.0 CAN_0connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/CAN_0] [get_bd_intf_ports CAN_0]</pre>*manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design***from the sources tab, select the BORA/BORAX block design (<code>bora${BASE_NAME}.bd</code> for Bora, <code>borax.bd</code> for BoraX) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''***on the next window, select ''Copy generated Let Vivado menage wrapperand auto-update'' to allow user edits and click ''OK''***this creates the Verilog file (<code>bora_wrapper${BASE_NAME}_wrapper.v</code> for Bora, <code>borax_wrapper.v</code> for BoraX). If this file is not automatically included in the project, add it using the ''Add sources'' option****select Add or create design sources and click ''Next''****select the <code>bora_wrapper>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/</code> directory 

*select the <code>bora_pinout${BASE_NAME}_pinout.xdc</code> and <code>bora_timings${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository*check that the option ''Copy constraints'' '' files into project '' is enableddisabled and click finish

*select the <code>generate_binary_bitstream.tcl</code> file from the <code>scripts </code> directory from the BORA repository*select ''File -The bitstream file is now present in <code> Export -<project_directory> Export Hardware''*on the next window, enable ''Include Bitstream'' and click ''OK''*now launch the SDK session to generate the FSBL, clicking on ''File -/<prj_name> Launch SDK''*For '''BELK <= 3.0runs/impl_1/${BASE_NAME}_wrapper.2''' bit</code> and '''BXELK <= 1code><project_directory>/<prj_name>.0runs/impl_1/${BASE_NAME}_wrapper.1''' : please follow the [[Creating_and_building_example_Vivado_project_(BELKbin</BXELK)#FSBL_project_build | FSBL build instructions]]*For '''BELK-4.0.0''' and '''BXELK-2.0.0''' there is no need to build FSBL. Instead PS configurations files are used to build U-boot binaries if necessarycode>.**Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora::<code>cp $PROJ_DIR<project_directory>/bora<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/ip/bora_processing_system7_0_0<prj_name>_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora${UBOOT_PS7_DIR}/</code>:*Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot_(BELK/BXELK) Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.

==FSBL project build== *once the Xilinx SDK is ready, perform the following operations from the GUI:**Click on ''File -> New -> Application Project''**select the Project Name: <code>bora_FSBL</code>**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..*from ''Browse...'' open the file <code><bora_repo>/patch/belk-sd-boot.patch</code>**Click ''Next''**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''bora_FSBL -> src''**Click ''Next''**Check that the patch is correctly applied to the source code and click on ''Finish''**'''Vivado v2014.4 only''': With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):***apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under ''bora_wrapper_hw_platform_0''***apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of the following options:**manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin</code>*this step is board dependent**configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>bora_FSBL</code> project and select ''C/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot):**select the <code>bora_FSBL</code> project in ''Project Explorer''**click on ''Xilinx Tools -> Create Zynq Boot Image''*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list. *otherwise, select ''Create new BIF file'' and set the output path and in ''Boot image partitions'' add the following files:**bora_FSBL.elf, which can be found in the project <code>Debug</code> directory. N.B. check that the <u>''Partition Type'' for FSBL is ''bootloader''</u>***<code>bora_wrapper.bit</code>, which is the bitstream generated by the Vivado project (<u>''Partition Type'' must be ''Datafile''</u>)**<code>u-boot.elf</code>, which is the compiled U-Boot with <code>.elf</code> extension (<u>''Partition Type'' must be ''Datafile''</u>)*in ''Output path'', select the path for the <code>BOOT.bin</code> file == Downloading the bitstream to the device ===

=== Helloworld from UART0 ===

dvdk@vagrant-ubuntu-trusty-64:~/bora/rfs/belk/home/root$ source ~/env.sh dvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0