!BELK /BXELK version

 <section begin=BELK/>=Introduction=Creating and building example Vivado project==BELK /BXELK provides an example Vivado project for BORA/BORAX /BORALITE boards. This project allows to:*generate FSBL binary imagethe PS configuration files to be used with U-boot SPL build

The project is stored is a git repository, as described [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]].

It is assumed that the Zynq development environment has been set up properly (see [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system|this page]] for more details).

===Command line based procedure==={{ImportantMessage|text=The following procedure is detailed for Bora boardmake use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM. <br>For BoraX board please replaceBora SoM use:*<code>bora_FSBLexport BASE_NAME=bora</code> with *<code>borax_FSBLexport UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>bora_wrapper_hw_platform_0</code> with <code>borax_wrapper_hw_platform_0export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora.sdk</code> with For BoraX SoM use:*<code>export BASE_NAME=borax.sdk</code>*<code>bora_wrapper.bit</code> with <code>borax_wrapper.bitexport UBOOT_PS7_DIR=borax</code>.

*copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/

*enter the git directory and launch the following command to set the project directory*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstreamgen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

. /opt/Xilinx/Vivado/2014.4<Vivado_version>/settings64.shvivado -mode tcl -source build_projectscripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*the <code>build_project</code> script allows user to select BORA or BORAX target*at At the end of the bitstream build process, the <code>build_projectbuild_prj_*</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*once the Xilinx SDK The bitstream file is ready, perform the following operations from the GUI:**Click on ''File -> New -> Application Project''**select the Project Name: <code>bora_FSBL</code>**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**apply the patch, right-clicking on bora_FSBL now present in Project Explorer and then clicking on Team -> Apply Patch..*from ''Browse...'' open the file <code><bora_repo>/patchvivado/belk-sd-boot${BASE_NAME}.patch<runs/impl_1/code>**Click ''Next''**Select ''Apply the patch to the selected file, folder or project'': and select <code>main${BASE_NAME}_wrapper.cbit</code> from ''bora_FSBL -> src''**Click ''Next''**Check that the patch is correctly applied to the source code and click on ''Finish''**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):***apply <code><bora_repo>/patchvivado/AR65145_ps7_init_c${BASE_NAME}.patch<runs/impl_1/code> on <code>ps7_init${BASE_NAME}_wrapper.cbin</code> under ''bora_wrapper_hw_platform_0''.*By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.**apply Copy the <code><bora_repo>/patch/AR65145_ps7_init_tclps7_init_gpl.patchc</code> on and <code>ps7_initps7_init_gpl.tclh</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of source files into U-boot source code directory using the following optionscommand example for Bora:**manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIRcp <bora_repo>/bora.sdkbd/SDK/SDK_Export${BASE_NAME}/bora_FSBLip/Debug/bora_FSBL.elf $PROJ_DIR{BASE_NAME}_processing_system7_0_0/boraps7_init_gpl.sdk* <U-boot_src_dir>/SDKboard/SDK_Exportdave/bora_FSBLbora/Debug${UBOOT_PS7_DIR}/bora_FSBL.bin</code>:*this step is board dependent**configure the automatic binary generation on project build. In ''Project Explorer'', rightFollow [[BORA_SOM/BELK-click on <code>bora_FSBL<L/code> project and select ''CDevelopment/C++ Build Settings'' and add the command <code>armBuilding_U-xilinxBoot | U-eabiboot build instructions]] to build U-objcopy -v -O binary ${ProjName}boot using new PS configurations.elf ${ProjName}.bin</code> on ''Post'Please note that the U-build steps''*create Boot binary images released along with BELK/BXELK were already built upon the <code>BOOTps7_init_gpl.binc</code> image (single file including FSBL, FPGA and U-boot for uSD boot):**select the <code>bora_FSBLps7_init_gpl.h</code> source files generated by the Vivado project described in this article''Project Explorer''**click on ''Xilinx Tools . As such, it is not generally required to rebuild U-> Create Zynq Boot Image''.:*if *The PS configurations are the project is correctly configured, the tool builds automatically same for Bora and BoraLite boards. ===GUI based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the component listed in correct ones according the form, so just add U-Boot to the listtarget SoM. <br>*otherwise, select ''Create new BIF file'' and set the output path and in ''Boot image partitions'' add the following filesFor Bora SoM use:*<code>export BORA_SOM=Bora</code>*bora_FSBL.elf, which can be found in the project <code>Debugexport BASE_NAME=bora</code> directory. N.B. check that the *<ucode>''Partition Type'' for FSBL is ''bootloader''export UBOOT_PS7_DIR=bora</ucode>**For BoraLite SoM use:*<code>bora_wrapper.bitexport BORA_SOM=BoraLite</code>, which is the bitstream generated by the Vivado project (*<ucode>''Partition Type'' must be ''Datafile''export BASE_NAME=boralite</ucode>)**<code>u-boot.elfexport UBOOT_PS7_DIR=bora</code>, which is the compiled U-Boot with For BoraX SoM use:*<code>.elfexport BORA_SOM=BoraX</code> extension (*<ucode>''Partition Type'' must be ''Datafile''export BASE_NAME=borax</ucode>)*in ''Output path'', select the path for the <code>BOOT.binexport UBOOT_PS7_DIR=borax</code> file}}

 *copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/

*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014201x.4y/settings32.sh</code>}}:

. /opt/Xilinx/Vivado/2014201x.4y/settings64.sh

*select the directory build project, insert the name of the project ''Project Name<prj_name>'' and click ''Next''

*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA${BORA_SOM}'' or ''BORAX'' depending on target SOM and click ''Next''

*in For the block design there are two possible ways:**Add the existing BD within the repo: ***select ''Add sources'' from the ''Flow Navigator''***click on ''Add or create design sources''***select Add Files and add <code><bora_repo>/bd/${BASE_NAME}/${BASE_NAME}.bd</code>***check that the Vivado GUI option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design'' from the ''Flow Navigator''***insert ''bora${BASE_NAME}'' (or ''borax'' in case of BoraX board) as ''Design name'' and click ''OK''***this creates a new block design. From the Diagram tab, add a new IP:****click the ''Add IP'' side button, or****click ''Add IP'' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar***check that ''Apply Board Preset'' is selected and click ''OK''****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins ***UART_0 and for CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 interfacesrespectively, otherwise correct manually***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design***from the sources tab, select the BORA/BORAX block design (<code>bora${BASE_NAME}.bd</code> for Bora, <code>borax.bd</code> for BoraX) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''***on the next window, select ''Copy generated Let Vivado menage wrapperand auto-update'' to allow user edits and click ''OK''***this creates the Verilog file (<code>bora_wrapper${BASE_NAME}_wrapper.v</code> for Bora, <code>borax_wrapper.v</code> for BoraX). If this file is not automatically included in the project, add it using the ''Add sources'' option****select Add or create design sources and click ''Next''****select the <code>bora_wrapper>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/</code> directory 

*select the <code>bora_pinout${BASE_NAME}_pinout.xdc</code> and <code>bora_timings${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository*check that the option ''Copy constraints'' '' files into project '' is enableddisabled and click finish

*select the <code>generate_binary_bitstream.tcl</code> file from the <code>scripts </code> directory from the BORA repository*select ''File -> Export -> Export Hardware''*on the next window, enable ''Include Bitstream'' and click ''OK''*The bitstream file is now launch the SDK session to generate the FSBL, clicking on ''File -> Launch SDK''*once the Xilinx SDK is ready, perform the following operations from the GUI:**Click on ''File -> New -> Application Project''**select the Project Name: present in <code>bora_FSBL<project_directory>/code>**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**this step is board dependent**apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -<prj_name> Apply Patch..*from ''Browse...'' open the file <code><bora_repo>runs/patchimpl_1/belk-sd-boot${BASE_NAME}_wrapper.patchbit</code>**Click ''Next''**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</codeproject_directory> from ''bora_FSBL -> src''**Click ''Next''**Check that the patch is correctly applied to the source code and click on ''Finish''**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):***apply <code><bora_repoprj_name>.runs/patchimpl_1/AR65145_ps7_init_c${BASE_NAME}_wrapper.patchbin</code> on <code>ps7_init.c</code> under ''bora_wrapper_hw_platform_0''***apply Copy the <code><bora_repo>/patch/AR65145_ps7_init_tclps7_init_gpl.patchc</code> on and <code>ps7_initps7_init_gpl.tclh</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of source files into U-boot source code directory using the following optionscommand example for Bora:**this step is board dependent** manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIRcp <project_directory>/bora<prj_name>.sdksrcs/SDKsources_1/SDK_Exportbd/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR{BASE_NAME}/bora.sdkip/SDK<prj_name>_processing_system7_0_0/SDK_Export/bora_FSBL/Debug/bora_FSBLps7_init_gpl.bin* <U-boot_src_dir>/code>**this step is board dependent**configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>bora_FSBL</code> project and select ''Cdave/bora/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjNameUBOOT_PS7_DIR}.elf ${ProjName}.bin/</code> on ''PostFollow [[BORA_SOM/BELK-build steps''*create the <code>BOOT.bin<L/code> image (single file including FSBL, FPGA and U-boot for uSD boot):**for Bora: select the <code>bora_FSBL<Development/code> project in ''Project Explorer''**click on ''Xilinx Tools Building_U-> Create Zynq Boot Image''*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add | U-Boot boot build instructions]] to the listbuild U-boot using new PS configurations. *otherwise, select ''Create new BIF file'' and set Please note that the output path and in ''U-Boot image partitions'' add binary images released along with BELK/BXELK were already built upon the following files:**bora_FSBL.elf, which can be found in the project <code>Debugps7_init_gpl.c</code> directory. N.B. check that the <u>''Partition Type'' for FSBL is ''bootloader''</u>**and <code>bora_wrapperps7_init_gpl.bith</code>, which is the bitstream source files generated by the Vivado project (<u>''Partition Type'' must be described in this article''Datafile''</u>)**<code>u-boot.elf</code>As such, which it is the compiled not generally required to rebuild U-Boot with <code>.elf</code> extension (<u>''Partition Type'' must be ''Datafile''</u>)*in ''Output path'', select the path for the <code>BOOT.bin</code> file