!BELK /BXELK version

 <section begin=BELK/>=Introduction=Creating and building example Vivado project==BELK /BXELK provides an example Vivado project for BORA/BORAX /BORALITE boards. This project allows to:*generate FSBL binary imagethe PS configuration files to be used with U-boot SPL build

This article describes how two build this The projectis stored is a git repository, as described [[BORA_SOM/BELK-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]]. Two procedures are described, the former  It is command line based while assumed that the latter is GUI basedZynq development environment has been set up properly (see [[BORA_SOM/BELK-L/Development/Build_system|this page]] for more details).

===Command line based procedure==={{ImportantMessage|text=The project is stored is a git repository, as described [[Build_system_(BELK)#Setting_up_the_Zynq_development_server_environment|here]]following procedure make use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM.<br>For Bora SoM use:*<code>export BASE_NAME=bora</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraX SoM use:*<code>export BASE_NAME=borax</code>*<code>export UBOOT_PS7_DIR=borax</code>}}

*copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/

*enter the git directory and launch the following command to set the project directory*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstreamgen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

. /opt/Xilinx/Vivado/2014.4<Vivado_version>/settings64.shvivado -mode tcl -source build_projectscripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*the <code>build_project</code> script allows user to select BORA or BORAX target*at At the end of the bitstream build process, the <code>build_projectbuild_prj_*</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*once the Xilinx SDK The bitstream file is ready, perform the following operations from the GUI:**Click on ''File -> New -> Application Project''**Select the Project Name: <code>bora_FSBL</code>**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**Apply the patch, right-clicking on ''bora_FSBL'' now present in Project Explorer and then by clicking on ''Team -> Apply Patch..''**From ''Browse...'' open the file <code><bora_repo>/patchvivado/belk-sd-boot${BASE_NAME}.patch<runs/impl_1/code>**Click ''Next''**Select ''Apply the patch to the selected file, folder or project:'' and select <code>main${BASE_NAME}_wrapper.cbit</code> from ''bora_FSBL -> src''**Click ''Next''**Check that the patch is correctly applied to the source code and click on ''Finish''**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):***Apply <code><bora_repo>/patchvivado/AR65145_ps7_init_c${BASE_NAME}.patch<runs/impl_1/code> on <code>ps7_init${BASE_NAME}_wrapper.cbin</code> under ''bora_wrapper_hw_platform_0''.*By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.**Apply Copy the <code><bora_repo>/patch/AR65145_ps7_init_tclps7_init_gpl.patchc</code> on and <code>ps7_initps7_init_gpl.tclh</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of source files into U-boot source code directory using the following optionscommand example for Bora:**launch this command manually :<code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIRcp <bora_repo>/bora.sdkbd/SDK${BASE_NAME}/SDK_Exportip/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR{BASE_NAME}_processing_system7_0_0/boraps7_init_gpl.sdk* <U-boot_src_dir>/SDKboard/SDK_Exportdave/bora_FSBLbora/Debug${UBOOT_PS7_DIR}/bora_FSBL.bin</code>:**configure the automatic binary generation on project Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-boot build instructions]] to buildU-boot using new PS configurations. In Project Explorer, right-click on ''bora_FSBL'' project, select CPlease note that the U-Boot binary images released along with BELK/C++ Build Settings and add BXELK were already built upon the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}ps7_init_gpl.elf ${ProjName}.binc</code> on ''Post-build steps''*create the and <code>BOOTps7_init_gpl.binh</code> image (single file including FSBL, FPGA and U-boot for uSD boot:**select source files generated by the ''bora_FSBL Vivado project'' described in this article''Project Explorer''**click on ''Xilinx Tools . As such, it is not generally required to rebuild U-> Create Zynq Boot Image''.:**if The PS configurations are the project is correctly configured, the tool builds automatically same for Bora and BoraLite boards. ===GUI based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the component listed in correct ones according the form, so just add U-Boot to the listtarget SoM.<br>*otherwise, select ''Create new BIF file'' and set the output path and in ''Boot image partitions'' add the following filesFor Bora SoM use:*<code>export BORA_SOM=Bora</code>*<code>bora_FSBL.elfexport BASE_NAME=bora</code>, which can be found in the project Debug directory. N.B. check that the *<ucode>''Partition Type'' for FSBL is ''bootloader''export UBOOT_PS7_DIR=bora</ucode>For BoraLite SoM use:*<code>export BORA_SOM=BoraLite</code>*<code>bora_wrapper.bitexport BASE_NAME=boralite</code>, which is the bitstream generated by the Vivado project (*<ucode>''Partition Type'' must be ''Datafile''export UBOOT_PS7_DIR=bora</ucode>)*For BoraX SoM use:*<code>u-boot.elfexport BORA_SOM=BoraX</code>, which is the compiled U-Boot with .elf extension (*<ucode>''Partition Type'' must be ''Datafile''export BASE_NAME=borax</ucode>)*in ''Output path'', select the path for the <code>BOOT.binexport UBOOT_PS7_DIR=borax</code> file.}} 

 *copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/

*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014201x.4y/settings32.sh</code>}}:

. /opt/Xilinx/Vivado/2014201x.4y/settings64.sh

*select the directory build project, insert the name of the project ''Project Name<prj_name>'' and click ''Next''

*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BORA${BORA_SOM}'' or ''BORAX'' depending on target SOM and click ''Next''

*in For the block design there are two possible ways:**Add the existing BD within the repo: ***select ''Add sources'' from the ''Flow Navigator''***click on ''Add or create design sources''***select Add Files and add <code><bora_repo>/bd/${BASE_NAME}/${BASE_NAME}.bd</code>***check that the Vivado GUI option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design'' from the ''Flow Navigator''***insert ''bora${BASE_NAME}'' as ''Design name'' and click ''OK''***this creates a new block design. From the Diagram tab, add a new IP:****click the ''Add IP'' side button, or****click ''Add IP'' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar***check that ''Apply Board Preset'' is selected and click ''OK''****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins ***UART_0 and CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'') and for selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 interfacesrespectively, otherwise correct manually***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design***from the sources tab, select the BORA/BORAX block design (<code>bora${BASE_NAME}.bd</code>) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''***on the next window, select ''Copy generated Let Vivado menage wrapperand auto-update'' to allow user edits and click ''OK''***this creates the Verilog file <code>bora_wrapper${BASE_NAME}_wrapper.v</code> file. If this file is not automatically included in the project, add it using the ''Add sources'' option****select Add or create design sources and click ''Next''****select the <code>bora_wrapper>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/</code> directory 

*select the <code>bora_pinout${BASE_NAME}_pinout.xdc</code> and <code>bora_timings${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository*check that the option ''Copy constraints'' '' files into project '' is enableddisabled and click finish

*select the <code>generate_binary_bitstream.tcl</code> file from the scripts directory from the BORA repository*select ''File -> Export -> Export Hardware''*on the next window, enable ''Include Bitstream'' and click ''OK''*now launch the SDK session to generate the FSBL, clicking on ''File -> Launch SDK''*once the Xilinx SDK is ready, perform the following operations from the GUI:**Click on ''File -> New -> Application Project''**Select the Project Name: <code>bora_FSBLscripts</code>**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**Apply directory from the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..BORA repository*From ''Browse...'' open the The bitstream file is now present in <code><bora_repoproject_directory>/patch<prj_name>.runs/<belkimpl_1/belkx>-sd-boot${BASE_NAME}_wrapper.patchbit</code>**Click ''Next''**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</codeproject_directory> from ''bora_FSBL -> src''**Click ''Next''**Check that the patch is correctly applied to the source code and click on ''Finish''**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):***Apply <code><bora_repoprj_name>.runs/patchimpl_1/AR65145_ps7_init_c${BASE_NAME}_wrapper.patchbin</code> on <code>ps7_init.c</code> under ''bora_wrapper_hw_platform_0''***Apply Copy the <code><bora_repo>/patch/AR65145_ps7_init_tclps7_init_gpl.patchc</code> on and <code>ps7_initps7_init_gpl.tclh</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of source files into U-boot source code directory using the following optionscommand example for Bora:**manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIRcp <project_directory>/bora<prj_name>.sdksrcs/SDKsources_1/SDK_Exportbd/bora_FSBL${BASE_NAME}/Debugip/bora_FSBL.elf $PROJ_DIR<prj_name>_processing_system7_0_0/boraps7_init_gpl.sdk* <U-boot_src_dir>/SDKboard/SDK_Exportdave/bora_FSBLbora/Debug${UBOOT_PS7_DIR}/bora_FSBL.bin</code>**configure the automatic binary generation on project build. In ''Project Explorer'', rightFollow [[BORA_SOM/BELK-click on <code>bora_FSBL<L/code> project and select ''CDevelopment/C++ Build Settings'' and add the command <code>armBuilding_U-xilinxBoot | U-eabiboot build instructions]] to build U-objcopy -v -O binary ${ProjName}boot using new PS configurations.elf ${ProjName}.bin</code> on ''Post'Please note that the U-build steps''*create Boot binary images released along with BELK/BXELK were already built upon the <code>BOOTps7_init_gpl.binc</code> image (single file including FSBL, FPGA and U-boot for uSD boot:**select the <code>bora_FSBLps7_init_gpl.h</code> source files generated by the Vivado project described in this article''Project Explorer''. As such, it is not generally required to rebuild U-Boot.**click on ''Xilinx Tools -> Create Zynq Boot Image''----{{notelist}} *if === Downloading the project is correctly configured, bitstream to the tool builds automatically all device ===Once the component listed in the formbitstream is ready, so just add U-Boot itself can be used to download it onto the listdevice. There are other options, however. *otherwiseFor more details, select ''Create new BIF file'' and set the output path and in ''please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot image partitions'' add #Introduction|this section]]. === Helloworld from UART0 ===Using the following files:**bora_FSBLFPGA bitstream previously created, it is possible to use serial tty port on Linux.elf, which can be found in the project The serial port is mapped to <code>Debug/dev/ttyPS1</code> directory. N.B. check that the (this is because <code>/dev/ttyPS0<u/code>''Partition Type'' is the console mapped to UART1). Here below an example on C code for FSBL is ''bootloader''initializing and using UART0 through FPGA: </upre>**#include <codestdio.h>bora_wrapper#include <stdlib.bith>#include </codestring.h>, which is the bitstream generated by the Vivado project (#include <uerrno.h>''Partition Type'' must be ''Datafile''#include </ufcntl.h>)**#include <codetermios.h>u int set_interface_attribs (int fd, int speed, int parity){ struct termios tty; memset (&tty, 0, sizeof tty); if (tcgetattr (fd, &tty) != 0) { printf("error %d from tcgetattr", errno); return -boot1; }  cfsetospeed (&tty, speed); cfsetispeed (&tty, speed);  tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8; // 8-bit chars // disable IGNBRK for mismatched speed tests; otherwise receive break // as \000 chars tty.c_iflag &= ~IGNBRK; // disable break processing tty.c_lflag = 0; // no signaling chars, no echo, // no canonical processing tty.c_oflag = 0; // no remapping, no delays tty.c_cc[VMIN] = 0; // read doesn't block tty.c_cc[VTIME] = 5; // 0.5 seconds read timeout  tty.c_iflag &= ~(IXON | IXOFF | IXANY); // shut off xon/xoff ctrl  tty.c_cflag |= (CLOCAL | CREAD);// ignore modem controls, // enable reading tty.elf<c_cflag &= ~(PARENB | PARODD); //code>shut off parity tty.c_cflag |= parity; tty.c_cflag &= ~CSTOPB; tty.c_cflag &= ~CRTSCTS;  if (tcsetattr (fd, TCSANOW, &tty) != 0) { printf("error %d from tcsetattr", which is the compiled Uerrno); return -Boot with 1; } return 0;}   int main(){ int fd; char *portname = "/dev/ttyPS1";  char msg[] = "Hello World from BELK (FPGA PS0 UART)!\n\r";  fd = open(portname, O_RDWR | O_NOCTTY | O_SYNC); if (fd <code>.elf0) { printf("error %d opening %s: %s", errno, portname, strerror (errno)); exit(1); } printf(msg);  set_interface_attribs (fd, B115200, 0); // set speed to 115,200 bps, 8n1 (no parity) write(fd, msg, strlen(msg));  exit(0);}  </codepre> extension ( and then compile it: <upre>''Partition Type'' must be ''Datafile''dvdk@vagrant:~/bora/rfs/belk/home/root$ source ~/env.sh dvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0</upre>)*in ''Output path'', select The program executed print out the path for msg string on the serial console and on <code>BOOT/dev/ttyPS1</code> port.bin<section end=BELK/code> file