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<div style= Bora Xilinx ZYNQ XC7Z010"clear:right; margin-bottom: .5em; float: right; padding: .5em 0 .8em 1.4em; background: none;">__TOC__</XC7Z020 CPU module =div>

Bora is the new top-class Dual Cortex-A9 + FPGA CPU module by DAVE, based on the recent [http[File://www.xilinx.com/content/xilinx/en/products/siliconBora5-devices/soc/zynq-7000small.html Xilinx Zynq XC7Z010/XC7Z020 application processorjpg|200px|frameless|border|left]]. Thanks to Bora, customers are going to save time and resources by using a compact solution that includes both a CPU and an FPGA, avoiding complexities on the carrier PCB.

Bora [http://www.dave.eu/products/zynq-bora BORA] is the new top-class Dual Cortex-A9 + FPGA CPU module by '''DAVE Embedded Systems''', based on the recent [http://www.xilinx.com/content/xilinx/en/products/silicon-devices/soc/zynq-7000.html Xilinx Zynq XC7Z010/XC7Z020 application processor]. Thanks to BORA, customers are going to save time and resources by using a compact solution that includes both a CPU and an FPGA, avoiding complexities on the carrier PCB. BORA is designed and manufactured according to '''DAVEEmbedded Systems'''s ''Ultra'' Line specifi cationsspecifications, in order to guarantee premium quality and technical value for customers who require top performances and flexibility. The [[Hardware Manual (Bora)]] provides detailed information about hardware interfaces and characteristics. This document will provide a functional overview of the module and will focus on system-related issues. Please visit [http://www.dave.eu/products/som/xilinx/zynq-XC7Z010-XC7Z020_bora BORA Web Page] for more product information.

For detailed information about Bora* Unmatched performance thanks to dual ARM Cortex-A9 @ 800 MHz* Up to 1 GB DDR3 SDRAM* All memories you need: on-board NOR and NAND Flash* Enabling smarter system thanks to Artix-7 FPGA integrated on chip* FPGA banks with Wide range of PSU input (from 1.2V to 3.3V)* Highest security and reliability: internal voltage monitoring and power good enable* Reduced carrier complexity: DUAL CAN, USB, Ethernet GB and native 3.3V I/O* Dual-CAN controller* Gigabit Ethernet LAN and additional GMII/MII interface* Up to 2x USB OTG* Up to 2x UART* Up to 2x I²C* Up to 2x SPI* Precise timing application thanks to on-board 5ppm RTC* Easy to fi t thanks to its Small form factor: 85mm x 50mm* Industrial (-40/+85°C) operating temperature range  == BORA technical specification =={| class="wikitable outercollapse" | width="100%"|{| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | CPU and Memories|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="center" style="background:#f0f0f0;"|'''Options'''|-| CPU||Xilinx Dual ARM Cortex-A9<br>ZYNQ XC7Z010/ZC7Z020 @ 800MHz |||-| Cache||L1: 32Kbyte instruction, 32Kbyte data<br>L2: 512Kbyte for each core |||-| RAM|| DDR3 SDRAM @ 533 MHz<br>Up to 1 GB |||-| SRAM|| On-chip RAM, 256 KB |||-| Storage||Flash NOR SPI (8, 16 MB)<br>Flash NAND (all sizes, on request - Up to 1GB) |||-|} {| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | Peripherals|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="center" style="background:#f0f0f0;"|'''Options'''|-| Coprocessors|| NEON™ & Single / Double Precision<br>Floating Point for each processor|||-| USB||Up to 2x 2.0 OTG ports |||-| UARTs||Up to 2x UART ports |||-| GPIO||Up to x lines, shared with other functions (interrupts available) |||-| Networks||Ethernet 10/100/1000 Mbps |||-| CAN||2x full CAN 2.0B compliant interfaces |||-| SD/MMC||2x SD/SDIO 2.0/MMC3.31 compliant controllers |||-| Serial buses||2x full-duplex SPI ports with three peripheral chip selects<br>2x master and slave I²C interfaces |||-| Timers||2x triple timers/counters (TTC) |||-| RTC ||On board (DS3232), external battery powered |||-| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) |||-|} {| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | Electrical, mechanical and environmentale spesifications|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="center" style="background:#f0f0f0;"|'''Options'''|-| FPGA model||Artix™-7|||-| Logic cells||28K to 56K|||-| LUTs||17K to 53K|||-| Flip flops||35K to 100K|||-| RAM||240KB to 560KB|||-| DSP slices||80 to 220|||-| Differential pairs||Up to 34 differential pairs for high freq. interfaces|||-|} {| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | Electrical, mechanical and environmentale spesifications|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="center" style="background:#f0f0f0;"|'''Options'''|-| Supply Voltage||3.3V, please on-board voltage regulation|||-| Active power consumption|| Please refer to the [[Hardware_Manual_(Bora)#Power_consumption | Power consumption]] section|||-| Dimensions||85mm x 50mm|||-| Weight|| |||-| MTBF|| |||-| Operating temperature||0..70 °C<br>-40..+85 °C|||-| Connectors||3 x 140 pins 0.6mm pitch|||}| [[File:Bora-bd.png|300px|center]]| * [http://www.dave.eu/products/som/xilinx/zynq-XC7Z010-XC7Z020_bora BORA Web Page]* [http://www.dave.eu/sites/default/files/files/bora-leaflet.pdf BORA leaflet]* [http://www.dave.eu/sites/default/files/files/bora-bd.pdf BORA Block Diagram]|} == Hardware Documentation == {| class="wikitable" |width="100%"| '''Electrical Schematics'''|* [[Hardware Manual (Bora )]]* [[Reset scheme (Bora)| Reset Block Diagram]]* [[RTC (Bora)|On board RTC specifications]]* [[Pinout (Bora)|BORA Electrical pinout]]| '''Mechanical Documentation'''|* [https://www.dave.eu/sites/default/files/files/bora.dxf.zip BORA 2D Mechanical Drawing (DXF format)]* [https://www.dave.eu/sites/default/files/files/bora_stp.zip BORA 3D Mechanical Drawing (STEP format)]|'''Carrier Board design'''| * [https://www.dave.eu/system/files/area-riservata/boraevb-2.2.0-BELK-dsn.zip Evaluation Board Electrical Schematics]* [[Carrier_board_design_guidelines_(SOM) | General carrier board design guidelines]]* [[Integration guide (Bora/BoraX)|BORA specific integration guidelines]]| '''Thermal & Power Management|''' * [[Thermal_management_guidelines | Thermal management guidelines]]* [[Power_consumption_(Bora)|Power consumption benchmarks]]* [[Power (Bora)|Power management guidelines]] article.|}

== Bora RSS Feed Software Documentation ==

Please visit refer to [http://www.dave.eu/products/zynq-bora Bora Web Page[BELK|this page]] for more product informationdetails.

== Bora Leaflet =Stay tuned with updates: BORA RSS Feed =

Please download it from subscribe to the following link: [http:/<newsfeedlink feed="Bora Pages Updates" format="rss">Bora Pages Updates</www.dave.eu/sites/default/files/files/Bora-leafletnewsfeedlink> RSS Feed using your favourite RSS reader to be notified on '''wiki pages updates related to BORA'''.pdf]

This category collects all the pages specific to Dido Bora modules and related carrier boards.