Carrier board design guidelines (SOM)

Info Box Applies to Naon Applies to Maya Applies to Lizard Applies to Diva

The information here provided are preliminary and subject to change.

Introduction

This page provides useful information and resources to system designers in order to design carrier boards hosting DAVE system-on-modules (SOM).

These guidelines are provided with the goal to help designers to design compliant systems with DAVE modules and they cover schematics and PCB aspects. They apply to several products that are listed on the top right corner of this page (see "Applies to" boxes).

Basics Guidelines

In this section basics hardware guidelines valid for all DAVE SOMs are analyzed.

Schematics

• Check mirroring and pinout for every connector on the board
• Check for TX and RX lines
• Add series resistors as interface needs (see interface details)
• TBD

PCB

PCB Tecnology

Use a PCB technology as advised in the following table

Parameter	Min	Typ	Max
Layers(number)	4	6	-
Power Plane Layers	2	-	-
Clearence(mils)	4	6	-
Vias hole (mechanical)	0,3		-
Minimum number of via for each power signal layer changes	2	3	-
Minimum number of via for each power signal SOM connector pin	1	2	-
Component package size	0402	0603	-
PCB Height(mm)	1,4	1,6	-

• If vias smaller than minimum advised size are used, take care to maintain an adeguate number of via when you change layer on each power signal.
  
• PCB heights less than minimum advised can produce PCB heating and mechanical issues
• Use Solid Connection for on plane vias

PCB Basics Guidelins

• Avoid stubs
• Isolate clock and HI-SPEED signal (differential lines i.e.) for at least two times trace width or gap for differential lines
• Avoid voids on planes

Interfaces Guidelines

This section provides guidelines for the most used interfaces on DAVE's SOMs module. Please refer to SOM's detailed pages for specific additional information.

Ethernet 10/100

Case #1: PHY is integrated on SOM

This section refers to the case of PHY integrated on SOM such as Lizard and Maya.

Schematics

• If LAN connector with integrated magnetic is used:
  • predispose some protection diodes on ethernet lines
  • Connect connector shield to an adeguate GND or shield Plane

PCB

Parameter	Min	Typ	Max
Differential Impedance(ohm)	76	95	114
Common Mode Impedance	46,75	55	63,25
Gap between TX and RX lines	2xseparation	2xseparation	-
Gap between other signal	2xseparation	4xseparation	-
Intra pair matching(mils)	0	25	240
TX and RX via mismatch	0	0	1
Max PCB trace length	-	-	3"

• Common differential impedance value is 100ohm
• If LAN connector with integrated magnetic is used:
  • do not route traces under the connettor, neither on opposite side
  • place filter diode near connector
  • place others signals far from connector.
  • Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
• If on board magnetic are used
  • adeguately isolate system GND from magnetic connector side
  • Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
• try to match as best as possible each differential pair (intrapair matching)
• no TX and RX matching required

Case #2: PHY is not integrated on SOM and a RGMII PHY is used

This section refers to the case of PHY is not integrated on SOM and a RGMII Gigabit Ethernet PHY is used.

Schematics

• Add series resistors (RPACK resistors recommended) to RGMII lines
• Properly decouple PHY Power Supplies rails
• Properly decouple every supply pin of Ethernet PHY
• Properly separate analog Supply Rails

PCB

Parameter for RGMII interface	Min	Typ	Max
Common mode impedance(ohm)	-	50	-
Gap between lines	2xW	-	-
Gap between other signal	4xW		-
Matching(mils)	-	250	-
Via Mismatch	0	0	1

Parameter for Gigabit Lines	Min	Typ	Max
Differential Impedance(ohm)	76	95	114
Common Mode Impedance	46,75	55	63,25
Gap between TX and RX lines	2xseparation	2xseparation	-
Gap between other signal	2xseparation	4xseparation	-
Intra pair matching(mils)	0	10	10
TX and RX via mismatch	0	0	1
Max PCB trace length	-	-	3"

• Ground and VCC planes must be as large as possible
• Avoid plane split and voids
• Place bypass capacitor near every PHY supply pin
• Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
• Place PHY device not too near to connector (250 mils reccomended distance)
• Keep MDIO clock signal isolated from other signals

Case #3: PHY is not integrated on SOM and a RMII PHY is used

This section refers to the case of PHY is not integrated on SOM and an RMII 10/100 Ethernet PHY is used.

Schematics

• If possible, place series resistor to RMII interface signals
• Properly decouple PHY Power Supplies rails
• Properly separate analog Supply Rails
• Properly decouple every supply pin of Ethernet PHY
• Use a standard RMII PHY that supports correct clock mode (see SOM specification for further details)

PCB

Parameter for RMII interface	Min	Typ	Max
Reccomended Common mode impedance(ohm)	-	50	-
Gap between other signal	2xW		-

• Since RMII signals are not critical such as RGMII, is not necessary a strong matching between lines.
• Avoid signal traces too long
• Avoid stubs

Parameter for Ethernet Lines	Min	Typ	Max
Differential Impedance(ohm)	76	95	114
Common Mode Impedance	46,75	55	63,25
Gap between TX and RX lines	2xseparation	2xseparation	-
Gap between other signal	2xseparation	4xseparation	-
Intra pair matching(mils)	0	25	240
TX and RX via mismatch	0	0	1
Max PCB trace length	-	-	3"

• Ground and VCC planes must be as large as possible
• Avoid plane split and voids
• Place bypass capacitor near every PHY supply pin
• Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
• Place PHY device not too near to connector (250 mils reccomended distance)
• Keep MDIO clock signal isolated from other signals