{{ObsoleteWikiPage|link==Introduction==DESK-XZ7-L}}

Bora Embedded Linux Kit ({{ImportantMessage|text='''For BELK for short) provides all 3.0.2 or older, the necessary components required to set up boot process was based on the developing environment for:* configuring the system FSBL+second-stage bootloader (PS and PLU-Boot) at hardware level* build combination. From BELK 4.0.0 on, the boot process is based on the first-stage bootloader (FSBLU-Boot SPL)* building the +second -stage bootloader (U-Boot)combination.'''* building and running Linux operating system on Bora-based systems* building Linux applications that will run on the target}}

'''DAVE Embedded Systems''' provides all the customization required (in particular at bootloader and Linux kernel levels) to enable customers use the standard Zynq-7000 development tools for building all the firmware<section begin="Unboxing" /software components that will run on the target system.>==Unboxing==

==Logical structure of Bora Embedded Linux Kit (BELKfor short)==provides all the necessary components required to set up the developing environment for:To understand * building the structure of first-stage bootloader:** FSBL for BELK, it is necessary to describe 3.0.2 or older** U-boot SPL for BELK 4.0.0 or newer* building the basic organization of Xilinx Vivado Design Suite/Xilinx SDK second-stage bootloader (U-Boot)* building and to recall briefly running Linux operating system on Bora-based systems* building Linux applications that will run on the recent history of development tools provided by Xilinxtarget.

===A little bit of history===At '''DAVE Embedded Systems''' provides all the time of this writing customization required (October 2013in particular at bootloader and Linux kernel levels) Xilinx is migrating from mature ISE 14.x Design Suite - that should be the last series of this suite - to enable customers to use the new Vivado environment. Both are composed by several programs and some of these are in common. From the general standpoint, the main difference between ISE and Vivado - even if ISE does support standard Zynq - is the the latter has been expressively conceived to support newer SOC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as the default environment 7000 development tools for BELK would seem building all the natural choice. However, firmware/software components that will run on the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suitetarget system. Plus Vivado is still a little bit <section end="greenUnboxing" and several bug fixes and improvements are introduced by every new release./>

{| class="wikitable" style==Structure of BELK reference designs=== The typical linux-based Zynq design is composed by the following parts"margin:auto;"* FSBL* U|-Boot* device tree file!Component* Linux kernel!Description* Root file system!Notes* Executable image of core #1 (in case of AMP systems)* FPGA bitstream. Generally speaking, this parts |- in the binary/sinthesized form - are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However in real world products, this may be too rigid because developers may want to handle these parts separately and independently.  ===Basic structure of Vivado Design Suite and integration into BELK| style===Vivado/SDK (1) can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA"text-related tools such as Floorplanner and pure-software development tools such as SDK.The ambitious objective is to provide a complete, user friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities (2). As usual this ease of use comes at the expence of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason BELK has been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to push the modularization and the maintainability of the projects to the maximum extent. The following pictures are retrieved from BELK Quick Start Guide and shows respectively the Vivado/SDK default development flow and how this has been integrated in the BELK infrastructure. align: center;" | [[File:Belk-vivado-sdkBora5-development-flowsmall.pngjpg|thumbnail|center|300px|Vivado/SDK development flow60px]]|[[File:Belk-vivado-sdk-integration.pngCategory:Bora|thumbnail|center|300px|Vivado/SDK integration into BELKBora]]  (1) The Software Development Kit (SDK) is the Xilinx Integrated Design Environment for creating embedded applications on Zynq™-7000 All Programmable SoCs. SDK is the first application IDE to deliver true homogenous and heterogenous multi-processor design and debug, it is optionally included with the Vivado Design Suite or ISE Design Suite, or available as a separate free download for application developers. (2) Nevertheless FPGA developers will find all the traditional tools that allow complete control of FPGA fabric.  == BELK software components == '''DAVE Embedded Systems''' adds to the latest Linux BSP from Xilinx the customization required to support the Bora platform, in particular at bootloader and linux kernel levels.SOM

The following table reports the XELK releases information.Default option is DBRF4110S2R (see [[#Order codes|Order codes]] for more options){| class=*SoC: Xilinx XC7Z020 (866Mhz, Speed "wikitable-3" , Tj 0-100°C)*SDRAM: 1 GB DDR3*NOR: bootable SPI flash 16 MB*NAND: 1GB (SLC)|!* For more details, please refer to the[[Hardware Manual (Bora) | Bora Hardware Manual]]!colspan=* By default, ARM cores frequency is set to 667 MHz and the [[Creating and building example Vivado project (BELK/BXELK)|example Vivado project]] is implemented for a "3-1" device. This choice makes the software released with the kit compatible with possible variants based on different SoM models. In this regard, see also the [[#Order codes| BELK versionorder codes section]].

|Release numberstyle="text-align: center;" |1[[File:Boraevb-02.0.0png|80px]]|1.1.0BORA Carrier board|2.0.0Se also the[[BoraEVB | BoraEVB]] page

|Statusstyle="text-align: center;" | [[File:Alimentatore.jpg|Released40px]]|ReleasedAC/DC Single Output Wall Mount adapter<br>Output: +12V – 2.0 A|ScheduledPlease refer to Belk Quick Start Guide

|Release date[[File:FTDI-CHIPI-X10.png|60px|July 2013center]]|November 2013FTDI USB/RS232 cable adapter<br>|1Q2014FTDI code: [https://ftdichip.com/products/chipi-x10/ CHIPI-X10]

|'''Release notes'''|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 1File:EVK-kit-DB9-serial-cable.0png.0 png| Ver 1.0.060px|center]]|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 1.1.0 | Ver 1.1.0]]D9 Female to D9 Female null modem cable| -

|SOM PCB version|CS020313A|CS020313A|CS020313B|--[[File:Sandisk_Industrial_32GB.png|Supported carrier boards60px|[[BoraEVB-Litecenter]]|[[BoraEVB-Lite]]MicroSDHC card|[[BoraEVB]]

|U-Boot version} ===Order codes==={|2013.04-belk-1.0.0class="wikitable" style="margin: auto;"|2013.04-belk-1.1.0+!Order code|t.b.a.!Description

|Linux version|3.9.0-bora-1.0.0|3.9.0-bora-1.1.0|t.b.a.|BELK- |Drivers|valign="top" | L-|valign="top" | S-S|valign="top" | -This code refers to the default configuration detailed above

<section end=== Release notes ==="Kit Content" />

==Logical structure of Bora Embedded Linux Kit (BELK)== Please refer to [[Logical_structure_of_Bora_and_BoraX_Embedded_Linux_Kits_(BELK 1/BXELK)|this page]].1.0 ====

Updates:# Switched to Vivado 2013.3# Added application note "AMP on Bora" ==BELK software components == Please refer to [[BELK 1/BXELK_software_components|this page]].0.0 ==== First official release ==Kit Contents==

{| class="wikitable" =Quick start guide==|-!Component!Description!Notes|-|style="text-align: center;" | Please refer to [[File:Bora5-small.jpgBELK/BXELK_Quick_Start_Guide|60pxthis page]].|Bora SOM<br>CPU: Xilinx Zynx 7000==Physical devices mapping==|Please refer to [[Hardware Manual Physical_devices_mapping_(BoraBELK/BXELK) | Bora Hardware Manualthis page]].|-==Advanced topics==|style="text-align: center;" | [[File:Boraevb-lite-01.png|80px]]|Bora-EVB-Lite Carrier board==Debugging with Eclipse===|Please refer to [[BoraEVB-Lite Debugging with Eclipse (MVM)| BoraEVB-Litethis page]] page.|-|style="text-align: center;" | [[File:Alimentatore.jpg|40px]]|AC/DC Single Output Wall Mount adapter<br>Output: +12V – 2.0 A==ConfigID feature===|Please refer to Belk Quick Start Guide|-|style="text-align: center;" | [[File:ProdSDC-MBLY-thumb.pngConfigID_management_(BELK/BXELK)|50pxthis page]]|MicroSDHC card with SD adapter and USB adapter|Please refer to Belk Quick Start Guide|-|}.

* Belk Quick Start Guide (available for BELK kit owners)[[BoraEVB | BORAEVB]]* Application Note: [http:[BELK//www.dave.eu/sites/default/files/files/an-belk-001-amp-linux-freertos.pdf AN-BELK-001: Asymmetric Multiprocessing (AMP) on Bora – Linux + FreeRTOSBXELK Quick Start Guide]]* [[FAQs_(Bora) | Bora BORA FAQs]]