{{ObsoleteWikiPage|link=DESK-XZ7-L}} {{ImportantMessage|text=Introduction'''For BELK 3.0.2 or older, the boot process was based on the FSBL+second-stage bootloader (U-Boot) combination. From BELK 4.0.0 on, the boot process is based on the first-stage bootloader (U-Boot SPL)+second-stage bootloader (U-Boot) combination.'''}} <section begin="Unboxing" />==Unboxing== [[File:Belk_01.png|500px]]

* configuring the system (PS and PL) at hardware level* build building the first-stage bootloader (:** FSBL)for BELK 3.0.2 or older** U-boot SPL for BELK 4.0.0 or newer* building the second -stage bootloader (U-Boot)

* building Linux applications that will run on the target.

Dave '''DAVE Embedded Systems''' provides all the customization required (in particular at bootloader and Linux kernel levels) to enable customers to use the standard Zynq-7000 development tools for building all the firmware/software components that will run on the target system.<section end="Unboxing" />

<section begin="Kit Content" />==Kit Contentscontents==

{| class="wikitable" style="margin: auto;"

|style="text-align: center;" | [[File:Bora5-small.jpg|60px]]|[[:Category:Bora |Bora]] SOM<br>CPU Default option is DBRF4110S2R (see [[#Order codes|Order codes]] for more options)*SoC: Xilinx Zynx 7000XC7Z020 (866Mhz, Speed "-3", Tj 0-100°C)*SDRAM: 1 GB DDR3*NOR: bootable SPI flash 16 MB*NAND: 1GB (SLC)|Please * For more details, please refer to the[[Hardware Manual (Bora) | Bora Hardware Manual]]* By default, ARM cores frequency is set to 667 MHz and the [[Creating and building example Vivado project (BELK/BXELK)|example Vivado project]] is implemented for a "-1" device. This choice makes the software released with the kit compatible with possible variants based on different SoM models. In this regard, see also the [[#Order codes|order codes section]].

|style="text-align: center;" | [[File:Boraevb-lite-0102.png|80px]]|Bora-EVB-Lite BORA Carrier board|Please refer to Se also the[[BoraEVB-Lite | BoraEVB-Lite]] page

|style="text-align: center;" | [[File:Alimentatore.jpg|40px]]

|style="text[[File:FTDI-CHIPI-alignX10.png|60px|center]]|FTDI USB/RS232 cable adapter<br>|FTDI code: [https: center;" //ftdichip.com/products/chipi-x10/ CHIPI-X10]|-| [[File:ProdSDCEVK-kit-DB9-serial-MBLYcable.png.png|60px|center]]| D9 Female to D9 Female null modem cable||-thumb| [[File:Sandisk_Industrial_32GB.png|50px60px|center]]|MicroSDHC card with SD adapter and USB adapter|Please refer to Belk Quick Start Guide

===Logical structure of Bora Embedded Linux Kit (BELK)Order codes===To understand the structure of BELK, it is necessary to describe the basic organization of Xilinx Vivado Design Suite/Xilinx SDK and to recall briefly the recent history of development tools provided by Xilinx.====A little bit of history=={| class="wikitable" style=At the time of this writing (October 2013) Xilinx is migrating from mature ISE 14.x Design Suite - that should be the last series of this suite - to the new Vivado environment. Both are composed by several programs and some of these are in common. From the general standpoint, the main difference between ISE and Vivado - even if ISE does support Zynq - is the the latter has been expressively conceived to support newer SOC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as the default environment for BELK would seem the natural choice. However, the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suite. Plus Vivado is still a little bit "greenmargin: auto;" and several bug fixes and improvements are introduced by every new release.|+!Order codeSince Bora was presented in 2013 and because this product addresses long longevity markets such as industrial and biomedical, DAVE chose to build BELK upon Vivado that undoubtedly represents today the future of Xilinx development environments.!Description|-====Basic structure of Vivado Design Suite and integration into |BELK====Vivado/SDK (1) can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA-related tools such as Floorplanner and pureL-S-software development tools such as SDK.SThe ambitious objective is to provide a complete, user friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities (2). As usual this ease of use comes at the expence of control and flexibility. |This could not be acceptable in many cases where engineers need to control and customize many aspects of the project code refers to implement what is required by system specifications. For this reason BELK has been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to push the modularization and the maintainability of the projects to the maximum extent.configuration detailed above|-The following pictures are retrieved from BELK Quick Start Guide and shows respectively the Vivado/SDK default development flow and how this has been integrated in the BELK infrastructure.|}

[[File:Belk-vivado-sdk-development-flow.png|thumbnail|center|300px|Vivado<section end="Kit Content" /SDK development flow]][[File:Belk-vivado-sdk-integration.png|thumbnail|center|300px|Vivado/SDK integration into BELK]]>

(1) The Software Development Kit (SDK) is the Xilinx Integrated Design Environment for creating embedded applications on Zynq™-7000 All Programmable SoCs. SDK is the first application IDE == BELK software components ==Please refer to deliver true homogenous and heterogenous multi-processor design and debug, it is optionally included with the Vivado Design Suite or ISE Design Suite, or available as a separate free download for application developers[[BELK/BXELK_software_components|this page]].

==Quick start guide==Please refer to [[BELK/BXELK_Quick_Start_Guide|this page]].==Physical devices mapping==Please refer to [[Physical_devices_mapping_(2BELK/BXELK) Nevertheless FPGA developers will find all the traditional tools that allow complete control of FPGA fabric|this page]].==Advanced topics=====Debugging with Eclipse===Please refer to [[Debugging with Eclipse (MVM)|this page]].===ConfigID feature===Please refer to [[ConfigID_management_(BELK/BXELK)|this page]].

* Belk [[BoraEVB | BORAEVB]]* [[BELK/BXELK Quick Start Guide ]]* [[FAQs_(available for BELK kit ownersBora)| BORA FAQs]]